Tom Kelliher, CS 240
Apr. 23, 2012
This documents shows the pin constraints for the 2's complement and electronic lock problems so that you can confirm the Pinout Reports. In addition, one of the Synthesize process properties must be changed for the 2's complement problem. This document also describes how to perform FPGA testing for these two problems.
comp2.exe
. Source code is
available for your inspection.
cd
in the command line window, navigate to the folder
containing the executable test program. Type its name and press Enter. It
will begin to run. It's operation should be self-explanatory.
T
is
BTN3
, K
is BTN2
, Lock
is BTN1
, and
Unlock
is BTN0
. Locked
is LD2
, Unlocked
is LD1
, and IgnoringInputs
is LD0
.
Signal | Location |
mclk | B8 |
pdb(7) | R10 |
pdb(6) | P10 |
pdb(5) | R11 |
pdb(4) | N11 |
pdb(3) | T12 |
pdb(2) | P13 |
pdb(1) | R13 |
pdb(0) | R14 |
astb | V14 |
dstb | U14 |
pwr | V16 |
pwait | N9 |
rgan(3) | F15 |
rgan(2) | C18 |
rgan(1) | H17 |
rgan(0) | F17 |
Signal | Location |
clk | B8 |
T | H13 |
K | E18 |
Lock | D18 |
Unlock | B18 |
Locked | K15 |
Unlocked | J15 |
IgnoringInputs | J14 |