Introduction to Sequential Logic; Latches
Tom Kelliher, CS 240
Mar. 28, 2012
First Xilinx assignment; re-scheduled exam.
Finished VHDL introduction.
- Sequential logic.
- SR latch.
- D latch.
- Combinational logic is nice but...
- Sequential logic: introduces notion of memory.
- Synchronous vs. asynchronous circuits.
There will always be some asynchronous elements in a circuit which interfaces
to the real world environment.
- Clock: frequency, period, edges, duty-cycle.
- How can we achieve memory?
This is the basic idea, to be modified for actual use.
- General model of a sequential circuit:
- Active low inputs.
- Operation: three valid, one invalid input.
- Transparent when clock is high.
Latched when clock is low.
- Problem with use in circuits: double clocking.
A solution: non-overlapping clocks. (Achieved with master-slave
- SR latches inconvenient when storing data from, say, an ALU.
- D latch stores data directly:
(Think of this as a logic primitive.)
Thomas P. Kelliher