Tom Kelliher, CS 240
25 points, recommended due date of April 27
The final deadline for this assignment is 12:00 pm on Friday, May 4.
X. When a given bit is input, the corresponding output bit is to appear on output
Z, on the same clock cycle (Mealy machine). A second input,
RESET, is used to reset the circuit to its initial state on the next rising clock edge (synchronous reset) so that the circuit is prepared to receive the next 2's complement number beginning with the next clock cycle.
Unlock. If the lock is in the locked state, the following sequence of button pushes will unlock the lock:
Unlock. Pressing the
Lockbutton will lock the lock and also cause it to forget any previously-entered button pushes. Should a button push sequence other than the above sequence be entered, the lock should ignore further inputs until the
Lockbutton is pushed. The lock has three outputs:
Implement your design in VHDL. Then, download your design to one of the FPGA boards, test your circuit, and report the result.
I won't make the Xilinx boards available until you're ready to use them. Please give me advance notice of when you plan to begin using the boards.