Tom Kelliher, CS 240
Apr. 9, 2010
So, you've synthesized your VHDL design and now it's time to implement it, generate the bitstream file, and download the bitstream into the FPGA to configure it according to your design. This document will take you through that process using the Xilinx and XSTOOLS software:
You can hold off on adding the buffers below until you're ready to download your design into a Xilinx board. However, I recommend you use the clock naming convention described below.
First off, you'll need to verify that you're using the correct device. In
the Sources for pane, verify that the device you're using is
xc2s50-5tq144-XST VHDL. If not, right-click on the line, choose
Properties, and set the properties as follows:
Due to their importance, clock signals require special handling. You will
need to add the following to your VHDL code. I will assume that you named
your external clock signal (the name given in the port list of the entity
clk_ext and that you are using the signal clk
internally to clock your flip-flops. (Otherwise, modify the following for
your naming convention.) Initially, you should tie clk to
clk_ext like so:
signal clk: std_logic; ... begin clk <= clk_ext;When it's time to add the buffers, comment-out your assignment to clk and add the following to the declarations section of your architecture body:
component ibuf port ( i : in std_logic; o : out std_logic); end component; component bufg port ( i : in std_logic; o : out std_logic); end component; -- clk is the internal clock name. Modify as necessary. signal clk_pad, clk : std_logic;Add this to the body of your architecture:
u1 : ibuf port map ( i => clk_ext, -- External clock name. Modify as necessary. o => clk_pad); u2 : bufg port map ( i => clk_pad, o => clk); -- Internal clock name. Modify as necessary.The clock signal that you will now use to control your flip-flops is
Assign Package Pinsin the Processes for Current Source window.
Be careful when filling in this information. Doing this incorrectly can result in damage to the FPGA board, the PC, or both. Not to mention what it will do to your wallet!
Implement Design. Your design will be implemented. Correct any errors. (If you neglect to add the VHDL for clock signals, you will receive several fatal errors at this point.)
+symbol before it. Find and open the
Pad Reportand confirm that your I/O signals were indeed constrained to the correct FPGA pins. If they were not, go back and correct your constraints.
Do not proceed until the Pad Report is correct.
Once you've added the VHDL for the clock signal, the behavioral VHDL simulation will no longer work properly. However, the Post-Translate VHDL simulation will, so use that instead if you need to perform further simulation.
You can do this to verify that the board is functioning correctly.
If the bitstream file was successfully downloaded, the decimal point on the seven-segment display will be lit. Anytime the decimal point is not lit, the FPGA is not correctly configured.