Using Xilinx ISE Tools
Tom Kelliher, CS 240
Mar. 22, 2010
This document will take you through some of the basic steps involved in
using the Xilinx ISE Tools:
I assume you will be able to open an existing project yourself. For all of
the following, run the Project Navigator tool from the Xilinx
ISE 9.1i tab. Your first step, before doing anything else, should be
to create a Xilinx folder on your G: drive.
- A typical design workflow.
- Creating a new VHDL project.
- Adding a library to a project (not always necessary).
- Creating VHDL modules.
- Synthesizing a VHDL design.
- Simulating a design.
- Printing simulation results.
These are the steps you will typically follow in creating and testing a
- Start Project Navigator and create a new project.
- Copy any necessary pre-existing source files to the project
directory. (This should be underneath your Xilinx directory.)
- From the Project menu, use Add Source to add any
pre-existing source files.
- Create any necessary libraries and move any appropriate VHDL package
files to them.
- Use New source under the Project menu to create any
new source files, whether they be VHDL or Test Bench Waveform. For VHDL
files, check for syntax errors and correct. Save your work.
- Synthesize your design. Correct any errors.
- Perform a behavioral simulation.
- As required, print VHDL source and simulation waveforms.
- From the File menu, choose New Project. A dialog box
- Fill-in the requested information. ``Project Location'' should
be your Xilinx directory on your G: drive. ``Project Name'' should be a
descriptive project name. ``Top Level Source Type'' should be
For the next dialog ``Family'' select
For ``Device'' select
XC2S50. For ``Package'' select
For ``Speed Grade'' select
-5. ``Simulator'' should be set to
You won't need to do this very often. One situation where you would have
to do this is if you use the
LCDF_VHDL library with structural
For example, before creating the
- From Project menu, choose New Source. Select ``VHDL
Library'' and fill in a library name. For example:
- The new library will be visible after selecting the
tab in the Sources window.
- Move the appropriate VHDL packages to the library by right-clicking
on their name and choosing
Move to Library....
lcdf_vhdl library, go to the course
home page and download
func_prims.vhd into your project folder.
From the Project menu, select Add Source and select this
in ``Sources in Project,'' right click on the file and select Move to
Library. Select the
- Once you've opened your project, you can double-click any .vhd file
in the Files tab window to open it in the editor.
- To create a new VHDL file and edit it, open the Project menu
and choose New Source. Select
VHDL module and fill in a value
for the ``File Name.''
- The next dialog box may save you some time when entering an entity's
port information. If you don't want to use this feature, move on.
- To check a module's syntax, select the module in the ``Sources for
Synthesis/Implementation'' window, Expand the ``Synthesize'' item in the
``Processes for Entity Name Window'' and double-click on ``Check
Syntax.'' Scroll through the ``Console'' window to locate any syntax
errors and correct.
Each time you change your source VHDL, you need to re-synthesize before
running simulation. (Synthesizing a design is similar to compiling a
- Select the appropriate VHDL module in the ``Sources for
- Double-click on ``Synthesize'' in the ``Processes for Current
- Correct any errors.
First, we use HDL Bencher to specify test vectors, then we use ModelSim to
simulate the design, using the test vectors as inputs.
Okay, here's where you test your design to determine if it behaves as
intended. Just as proper selection of test cases is critical in debugging
a program, proper selection of test vectors is critical in debugging a
- First, if you've made any VHDL changes, re-synthesize your design.
- From the Project menu, choose New Source. Select
``Test Bench Waveform'' and choose a file name.
- In the next dialog box, make sure the waveform is associated with the
correct VHDL entity.
- Select appropriate settings in the Initial Timing dialog box.
- HDL Bencher should now be running. You use this tool to specify your
test vectors. Click on the blue fields to set the input waveforms.
Once you're finish, save your work and close HDL Bencher.
- Back in Project Navigator, change the "Sources for" selection to
Behavioral Simulation and select your test bench waveform file
from the ``Sources for Behavioral Simulation'' window. In the
``Processes for Entity Name'' window, expand the ``ModelSim
Simulator'' branch and double-click on ``Simulate Behavioral VHDL
- ModelSim will begin to run and open several windows. Watch the
``ModelSim XE III'' window for messages. Assuming all went well, the
input and output waveforms will be visible in the ``Wave'' window.
Undock this window, select the View menu, choose Zoom,
and select Zoom Full to see the entire simulation.
- When you're finished, close the ``ModelSim XE II'' window to close
all the ModelSim windows.
- Back in Project Navigator, you can double-click on the Test
Bench Waveform file in order to edit the test vectors.
In the ModelSim ``Wave'' window, open the File menu and choose Print. It's customary to print waveforms in landscape mode. This can
be chosen by clicking the Setup button. You also generally want
your waveform to occupy as few pages as possible, but still be readable.
Thomas P. Kelliher