Design three 64-bit adders, including figures showing the connections
What is the delay, in units of gate delays, for each of the three adders?
Include figures showing the delay models you are using for the one-bit
full adder, the four-bit carry-lookahead adder, and the carry-lookahead
- A ripple carry adder using 64 one-bit full adders.
- A partial carry-lookahead adder, using 16 4-bit carry-lookahead
adders. Carries ripple between the 4-bit adders.
- A full carry-lookahead adder.
How would the delays for your three adders generalize to an -bit adder?