Tom Kelliher, CS 240
Apr. 5, 2010
Assignment due Friday.
Sequential circuits and latches.
Sequential circuit analysis.
Must use two-phase, etc. clocking.
Clocked SR latch:
Analyze Q, !Q with these input waveforms. Assume Q low initially.
Master-Slave device: ensures no transparency. While master (leading latch) is transparent, slave is latched and vice-versa.
When J and K are both high, toggles in a controlled manner.
Analyze P, !P, Q, and !Q with these input waveforms. Assume Q low initially.
Changes state on edge, but not edge-triggered: one's catching.
Edge-triggered: samples input only during a clock transition.
Rising edge triggered D flip-flop. Figure 5-12 uses eight NAND gates and three inverters (verify for yourself). A slight improvement:
Analyze Q, !Q, !R, !S, T, and U with these input waveforms. Assume Q low initially.
Any one's catching?
Compact way of representing flip-flop behavior.
Clock edge is implied in the transition from to .
Always loads. To control loading, use this circuit:
Gating the clock signal leads to problems.