Inside RAM

Tom Kelliher, CS 240

May 7, 2008

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Final: Tuesday, May 13, 3:00-5:00 pm.

Assignment

None.

From Last Time

Introduction to memory; ROM; FLASH.

Outline

  1. Introduction.

  2. Static RAM.

  3. Dynamic RAM.

Coming Up

Final.

Introduction

  1. Organizations of RAMs: number of words, bits/word.

  2. Operation:
    1. Not enabled: low power mode, output in high-impedance state (disconnected)

    2. Read: A single word should be read. Address may change.

    3. Write: A single word should be written. Address must be stable.

    4. Refresh. Hidden or not hidden?

  3. RAM will have a 2-D structure: row/word, column/bit.

    The number of columns may not have anything to do with bits/word -- many RAMs have 1 bit/word but are 2-D internally.

  4. RAMS consist of:
    1. Storage cells.
    2. Word and bit decoders.
    3. Write logic.
    4. Read logic (sense amp).
    5. Refresh logic for DRAMs.

Static RAM

  1. Memory cell model:

    \includegraphics{Figures/sRamCell.eps}

    Goal: cell should be as small as possible, to increase storage density.

    Think about the AND gates on the output side as tri-state buffers -- transmission gates.

  2. Bit slice of a RAM array:

    \includegraphics{Figures/sRamSlice.eps}

  3. Assume you have $4 \times 1$ bit-slice RAM cells. Adding 2-to-4 decoders, how would a $4 \times 4$ RAM look? A $16 \times 1$ RAM?

Dynamic RAM

  1. DRAM cell:

    \includegraphics{Figures/dRamCell.eps}

  2. SRAM cell: five or six transistors. DRAM cell: one transistor and one capacitor.

  3. Bit-Slice: support structure similar.

  4. Bit line has higher capacitance than storage capacitor -- sense amps.

  5. Destructive read. Use of sense amps to restore data.

  6. Refresh due to leakage. Refresh logic.



Thomas P. Kelliher 2008-05-05
Tom Kelliher