Integrated Circuit Technology

Tom Kelliher, CS 240

Feb. 15, 2006

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Assignment

Read 3.1-3.

From Last Time

NAND gates, two-level implementation, parity.

Outline

  1. Terminology.

  2. Transmission gates.

  3. CMOS.

Coming Up

Combinational logic design process and simulation.

Terminology

  1. Today's important logic families: TTL, CMOS, LVTTL.

    Voltage, current, power, speed.

  2. Fan-in, fan-out.

  3. Noise margin. Where does noise come from?

  4. Power dissipation. Who cares? Extended battery, device life.

  5. Propagation delay. Don't forget about wires: on-chip and off-chip.

    Delay may be asymmetric: $t_{phl}$, $t_{plh}$. Max of both: $t_{pd}$.

  6. We'll only examine positive logic and transport delay.

Transmission Gates

An electronic switch:

\begin{figure}\centering\includegraphics[]{Figures/tg.eps}\end{figure}

Typically used to enable writes onto a bus. For examples, two CPUs sharing a memory bus. Bus arbitration.

\begin{figure}\centering\includegraphics[]{Figures/bus.eps}\end{figure}

Can be used in more crafty ways: viewing an EXOR as a ``conditional inverter:''

\begin{figure}\centering\includegraphics[]{Figures/exor.eps}\end{figure}

Eight transistors; two gate delays.

The standard NAND implementation requires four gates (16 transistors) and has a propagation delay of three gate delays.

CMOS

CMOS Transistors

  1. N-type transistor:
    1. Passes GND well.

    2. Degrades Vdd.

    3. Normally open switch.

  2. P-type transistor:
    1. Passes Vdd well.

    2. Degrades GND.

    3. Normally closed switch.

Diagrams:

\begin{figure}\centering\includegraphics[]{Figures/transistors.eps}\end{figure}

  1. Terminals: gate, drain, source.

  2. High capacitance on the gate.

CMOS Logic Gates

A CMOS inverter:

\begin{figure}\centering\includegraphics[]{Figures/inverter.eps}\end{figure}

A CMOS transmission gate:

\begin{figure}\centering\includegraphics[]{Figures/cmosTG.eps}\end{figure}

A CMOS 2-input NAND gate:

\begin{figure}\centering\includegraphics[]{Figures/nand.eps}\end{figure}

What determines power dissipation? Switching frequency.

Why transport delay isn't a good model: It takes time to move the charge on the gate. This is correctly modeled with inertial delay.


Thomas P. Kelliher 2006-02-14
Tom Kelliher