Overview of Pipelining

Tom Kelliher, CS 240

Jan. 28, 2000

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Assignment

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Examples of pipelines.

Outline

1. Overview of pipelining: comparison of single-cycle and pipelined implementations. Execution example.

2. Pipelining: a pipelined datapath. Hazards.

Coming Up

More Pipelines.

Overview of Pipelining

Comparison of Single-Cycle and Pipelined Performance

Assume:

1. Memory access is 2 ns.

2. ALU use is 2 ns.

3. Register file access is 1 ns.

Instruction class times:

Clock periods for the two implementations?

Execution example:

Note that pipelined register file reads are done during the second half of the clock cycle and writes are done during the first half. Why?

Consider the speedup:

1. Assumption: Stages are of equal length. What if they aren't?

2. Speedup is at most the number of pipeline stages.

   Do we achieve that?

   Consider the execution of 1,000 instructions and compute the actual speedup.

   What happened? The cost of the pipeline registers.

Consider:

1. How does the speedup occur?

2. Shortened instruction execution time?

3. Higher instruction bandwidth?

4. Conditional branches.

Pipelining

A pipelined datapath:

Consider four instructions: R-mode, a branch, LW, SW.

Observations:

1. Not a true pipeline: feedback.

2. How do we re-design control?

Hazards

1. Structural hazards.

   Example: unified L1 cache/memory.

2. Control hazards. Consider the following example:

   

   Solutions:

   1. Stall.

   2. Predict.

      Static prediction. Truly static. Compile-time determined.

      Dynamic prediction. Branch history tables. One-, two-bit counters.

   3. Delayed branch.

      Assumes you know branch outcome early.

      Code scheduling:

      

   Consideration: deeper pipelines.

3. Data hazards.

   Data not available when needed.

   ALU example:

   

   Fixed by forwarding.

   Memory example:

   

   How can this be fixed?