Overview of Pipelining

Tom Kelliher, CS 240

Jan. 24, 2000

Administrivia

Announcements

Assignment

From Last Time

Review of single- and multiple-cycle implementations

Outline

1. Overview of pipelining.

Coming Up

Pipelining.

Overview of Pipelining

Experimental observations:

1. If we hadn't pipelined, would it have taken longer?

2. Did pipelining decrease the time it took an individual to move through the line?

   How did the speedup occur?

3. Suppose at the end of the line we had two choices (say, ice cream and pie), you could choose only one at the beginning of the line, and we had the risk of running out.

   What could happen?

The laundry analogy:

The five stage MIPS pipeline --- designed to promote pipelining:

1. Instruction fetch.

   All instructions same length.

2. Decode and read registers.

   The consistent placement of the source registers permits this.

3. Execute ALU operation or calculate an address.

4. Access memory.

   Use of L1 caches to reduce contention.

5. Result write-back.

   Multiple reads/write.

Comparison of Single-Cycle and Pipelined Performance

Assume:

1. Memory access is 2 ns.

2. ALU use is 2 ns.

3. Register file access is 1 ns.

Instruction class times:

Clock periods for the two implementations?

Execution example:

Note that pipelined register file reads are done during the second half of the clock cycle and writes are done during the first half. Why?

Consider the speedup:

1. Assumption: Stages are of equal length. What if they aren't?

2. Speedup is at most the number of pipeline stages.

   Do we achieve that?

   Consider the execution of 1,000 instructions and compute the actual speedup.

   What happened? The cost of the pipeline registers.

Consider:

1. How does the speedup occur?

2. Shortened instruction execution time?

3. Higher instruction bandwidth?

4. Conditional branches.