Binary Addition, Subtraction, and Multiplication

Tom Kelliher, CS 220

Nov. 4, 2009

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Assignment

Read 3.5, 3.7.

From Last Time

Project discussion.

Outline

1. Binary Addition.

2. Binary Subtraction.

3. Overflow.

4. Binary Multiplication.

Coming Up

Floating point.

Binary Addition

1. Similar to decimal addition.

2. Nomenclature: ${\rm Augend} + {\rm Addend} = {\rm Sum}$

3. Eight bit example: 0x15 + 0x4C.

Binary Subtraction

1. Nomenclature: ${\rm Minuend} - {\rm Subtrahend} = {\rm Difference}$

2. To subtract, we add. How?

3. Eight bit example: 0x15 - 0x4C.

Overflow

1. In eight bits, consider 0x7F + 0x1. Augend and Addend are positive, but the sum is negative.

   How can this be?

   Would we have this result if we were working in 16 bits?

2. Overflow: when the sign of the result is wrong.

3. If we are adding two numbers of different signs or subtracting two numbers of the same sign, we will not have overflow. Why?

4. Overflow cases:

   Operation	A	B	Overflow Result
   $A + B$	$\geq 0$	$\geq 0$	$< 0$
   $A + B$	$< 0$	$< 0$	$\geq 0$
   $A - B$	$\geq 0$	$< 0$	$< 0$
   $A - B$	$< 0$	$\geq 0$	$\geq 0$

5. Addition logic:

   if the signs of A and B are the same
      if the signs of A and Sum are different
         overflow has occured.
   

   Subtraction is similar.

   A compact way of writing this in C:

   if (a ^ b >= 0 && a ^ sum < 0)
      overflow();
   

6. Overflow and programming languages:
   1. C: no overflow exceptions. Uses addu, etc.

   2. FORTRAN: overflow exceptions. Uses add, etc.

   What's an exception?

Binary Multiplication

1. Consider paper and pencil binary unsigned multiplication:
   1. Shift multiplicand left one bit position after each add/hold cycle.

   2. Add/hold depending upon current multiplier bit (examine lsb; shift right).

   3. Example: $1101 \times 0110$.

   4. Multiplying two $n$-bit numbers results in a $2n$-bit result.

2. Naive 32-bit shift-and-multiply hardware:
   

   How many bits in the datapath? Demonstrate on board.

   Running time?

3. Observation: Shifting multiplicand left and keeping partial product stationary is equivalent to keeping multiplicand stationary and shifting partial product right.
   1. Bonus 1: only 32-bits are added at any one time.

   2. Bonus 2: the multiplier can be stored in the unused part of the partial product register.

   More sophisticated 32-bit shift-and-multiply hardware:
   

   Demonstrate on board.

4. Optimal running time: O$(\log n)$, achieved with tree of carry-save adders with CLA adder at root.

Tom Kelliher