Operations, Operands, and Instructions

Tom Kelliher, CS 240

Sept. 2, 2005

Administrivia

Announcements

Assignment

Read 2.5-2.6.

From Last Time

Introduction

Outline

1. Simple arithmetic operations

2. Operands: registers, memory.

3. R-Format and I-Format instruction formats.

Coming Up

Logical and conditional instructions in MIPS.

Arithmetic Instructions

Instruction semantics:

add a, b, c        # This, BTW, is a comment.
sub a, a, b

De-compile into a single HLL statement:

add a, b, c
add a, a, d
add a, a, e

Compile each of the following:

a = b + c;
d = a - e;
f = (g + h) - (i + j);

Instruction Operands

Where are the operands?

Registers

$0 to $31 or $s0, $t0, etc.

Example:

add $1, $2, $3

Properties of registers:

1. Number of registers. 32 for MIPS, including the hardwired register. Two ways of naming: numbers, convention ``nicknames''. Why not more? Size of register file, size of operand fields within instructions.

   Other register files: x86, SPARC and the register window (Berkeley RISC, about 128 registers, spilling).

   Register renaming: ISA registers vs. physical registers.

2. Number of bits/register. 32. Word size.

   Implications: size of address space, datapath width.

3. General purpose vs. special purpose.

   MIPS, M68000, x86.

Using MIPS Registers

See pg. A-24 (CD) for the full register naming convention. Note the limited number of s and t registers.

Our simple convention:

1. Use $s0, $s1, etc. for C variables.

2. Use $t0, $t1, etc. for temps.

Recall:

f = (g + h) - (i + j);

Assume f through j are in $s0 through $s4, respectively. Compile the statement.

Memory

1. HLL have complex data structures such as arrays and structs. How are they handled?

2. Data transfer instructions: load, store. operands: memory address, register.

3. Actual MIPS instructions: lw, sw.

   Base and offset addressing: lw $s0, 8($s1)

4. MIPS memory is byte addressable, so word addresses differ by 4:
   

5. Endianess:
   1. Big endian machines: HP PA-RISC, IBM Power, MIPS, SPARC.

   2. Little Endian: x86.

   3. MIPS can go either way!

Compile the following:

g = h + A[8];

where g is in $s1, h is in $s2, and the base address of A, an array of 100 words, is in $s3.

Base, offset addressing.

Compile each of the following:

A[12] = h + A[8];

A[j] = h + A[i];

Notes:

1. Base, offset addressing, using constant offsets, is similarly useful for accessing members of structures.

2. Variables in registers are simpler to use and faster than variables in memory. Compilers must be clever in optimizing register use. Spilling registers.

Example:

lw $1, 4($0)
lw $2, 8($0)
add $1, $1, $2
sw $1 0($0)

Instruction Formats

MIPS R-Format

Example instruction: add $s2, $s0, $s1

Fields:

1. Op: Opcode.

2. Rs: First source operand.

3. Rt: Second source operand.

4. Rd: Destination operand.

5. Shamt: Shift amount -- ignore for now.

6. Func: Function. Further specification of the opcode.

In assembly: Op/Func Rd, Rs, Rt

Notes:

1. Memorize field positions and sizes for all three formats. Necessary later.

2. Example encodings:

   Assembly	Op	Rs	Rt	Rd	Shamt	Func
   add $1, $2, $3	0	2	3	1	0	32
   sub $4, $5, $6	0	5	6	4	0	34

MIPS I-Format

1. How do we fit Memory instructions into r-format? We can't!

2. Design principle 3: Good design demands good compromises.

3. Introduce another format -- added complexity tradeoff.

Example instruction: lw $s0 8($s1)

Fields:

1. Op: Opcode.

2. Rs: Source register.

3. Rt: Destination register.

4. Address: 16-bit signed immediate value.

   Offset range?

In assembly: Op/Func Rt, address(Rs)

Notes:

1. This format also used for immediate operands: addi $1, $2, 123.

2. Example encodings:

   Assembly	Op	Rs	Rt	Address
   lw $1, 1000($2)	35	2	1	1000
   sw $3, -12($4)	43	4	3	-12

Tom Kelliher