Building a Simple MIPS Datapath

Tom Kelliher, CS 220

Nov. 4, 2005

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Assignment

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From Last Time

Comparing performance.

Outline

  1. Quick introduction to digital logic.

  2. Overview of the MIPS implementation.

Coming Up

Completing the datapath.

Quick Introduction to Digital Logic

(Register for CS 240 for the complete introduction.)

Combinational Logic

  1. Basic logic gates: Inverter, AND, OR.

  2. One bit full adder:
    1. From truth table to gates.

    2. Multiple bit adders.

  3. 2-1 mux:
    1. What is it and why do we need it?

    2. From truth table to gates.

Sequential Logic and Examples

  1. The clock signal.

    \begin{figure}\centering\includegraphics[]{Figures/clock.eps}\end{figure}

    Sequential elements are rising edge sensitive.

  2. Clocking registers.

    \begin{figure}\centering\includegraphics[]{Figures/register.eps}\end{figure}

  3. A simple pipeline.

    \begin{figure}\centering\includegraphics[]{Figures/mad.eps}\end{figure}

  4. A loadable counter.

    \begin{figure}\centering\includegraphics[]{Figures/ldCnt.eps}\end{figure}

    \begin{figure}\centering\includegraphics[]{Figures/cntWave.eps}\end{figure}

Overview of the MIPS Implementation

Instruction set subset we'll consider:

  1. lw/sw.

  2. add, sub, and, or, slt.

  3. beq.

  4. j.

The general instruction cycle:

  1. Instruction fetch.

  2. Instruction decode.

  3. Register fetch.

  4. Operate.

  5. Register store or memory operation.

How do the steps of the cycle fit each of the three instruction classes: arithmetic-logic, memory reference, branch?

A high level view of the implementation, in view of the instruction cycle:

\begin{figure}\centering\includegraphics[width=6in]{Figures/mipsBlock.eps}\end{figure}

  1. Datapath only.

  2. Is everything we need for our instructions here?

  3. Why two memories?


Thomas P. Kelliher 2005-11-01
Tom Kelliher