NAND, Two-Level Implementations, Parity

Tom Kelliher, CS 220

Sept. 24, 2001

Administrivia

Announcements

Assignment

Read 2.8.

From Last Time

Simplifying K-maps.

Outline

1. NAND gates.

2. Two-level physical realizations.

3. Parity generation and checking.

4. BCD to 7-segment decoder example.

Coming Up

Circuit technologies.

NAND Gates

1. Not AND. Symbol. Truth table.

2. At the physical level, this is what we work with.

3. Completeness: Given a two-input NAND show how to implement inverter, AND, OR.

4. NOR completely analogous.

Physical Realizations

Given that we only have NAND gates, implement: ABC + DEF + GHI. (Draw using AND and OR, derive NAND implementation, and draw.)

Parity Generation and Checking

1. EXOR symbol, truth table.

2. EXOR = odd function. (NEXOR = even)

3. A ``big'' EXOR can be recursively constructed from ``small'' EXORs.

4. Parity generate and check circuit for ASCII data:

   

   Show a few examples.

Example: BCD to 7-Segment Decoder

Simplify and implement .