Interrupts Wrap-Up, Midterm 2 Review

Tom Kelliher, CS26

Oct. 31, 1996

  1. Collect homework.

  2. Finish last lecture.

Motorola 68000 Interrupts

Hardware Organization:

  1. Seven priority levels.

  2. Three-bit mask level in status word. Mask requests at same or lower level.

  3. Level seven is unmaskable.

  4. When interrupt is accepted:
    1. Processor enters supervisor state.

    2. Status word pushed on supervisor stack.

    3. PC pushed on supervisor stack.

    4. Mask level raised to level of interrupt.

    5. If auto-vectoring, get handler address from fixed location in vector table. Otherwise, read vector number from D7--D0 and get handler address from vector table. Load PC with handler address.

    6. Auto-vectoring: what and why?

  5. Handler executes RTE to return, restoring PC, PS, and privilege level.

  6. Vector table starts at address 0.

  7. Each entry in vector table is four bytes.

Example: Keyboard buffering

  1. Assume keyboard has no internal buffer, so processor has to provide software buffer.

  2. Assume type-ahead is nice.

  3. Assume polling is bad.

  4. Assume keyboard is ``dumb,'' so auto-vectoring is used.

  5. Keyboard uses IRQ2, which uses location 0x68 (auto-vector 2) in vector table

  6. Keyboard is memory mapped, using locations DATAIN, DATAOUT, and STATUS.

  7. Keyboard buffer is LINE.

INTVEC      EQU $68                 // Location in vector table.
INTEN       EQU $40                 // Keyboard int. enable.
INTDIS      EQU 0                   // Keyboard int. disable.
NEWPS       EQU $0100               // 68000 int. mask.
RTRN        EQU $0D                 // ASCII for carriage return.


            MOVE.L #READ, INTVEC    // Initialization.
            MOVE.L #LINE, PNTR
            MOVE.B #INTEN, STATUS
            MOVE.L #NEWPS, -(A7)    // Load correct mask and PC
            MOVE.L #MAIN, -(A7)     // and enter user privilege level.

MAIN        ...

// Keyboard interrupt handler.

READ        MOVEA.L A0, -(A7)       // Save register.
            MOVEA.L PNTR, A0
            MOVE.B  DATAIN, (A0)+
            MOVEA.L A0, PNTR
            CMPI.B  #RTRN, -1(A0)
            BNE DONE
            MOVE.B #INTDIS, STATUS  // Process line of input.
            BSR TEXT
DONE        MOVEA.L (A7)+, A0

Midterm 2 Review

  1. Combinational logic circuits: gates, truth tables, SOP form, bit-wise operations and masking.

  2. Circuit synthesis and Karnaugh maps.

  3. Multiplexers, decoders.

  4. Sequential circuits: latches, types of flip-flops, registers, register files.

  5. Timing: propagation delays, set-up, hold.

  6. Instruction execution:
    1. Instruction cycle.

    2. Addressing modes.

    3. Internal CPU bus structures.

    4. Internal CPU registers: IR, PC, MAR, MDR, etc.

    5. Fundamental sub-operations: memory transfers, register transfers.

    6. Memory interface.

  7. Controller organization: hardwired vs. microcode (control store, uPC, branching, ``subroutines.''). The effect of technology on organization.

  8. Pipelining and superscalar operation.

  9. Harvard architecture and execution stalls.

  10. External bus organization, memory-mapped I/O, non-memory-mapped I/O.

  11. Interrupts.

Thomas P. Kelliher
Wed Oct 30 11:53:16 EST 1996
Tom Kelliher