I/O Devices and Interrupts
Tom Kelliher, CS26
Oct. 29, 1996
- Questions on the homework?
- Midterm in 1 week.
- Will review on Thursday and wrap-up 4.1--4.3.
- Printer (serial, parallel)
- Expansion cards:
- Video adapter.
- Ethernet card.
- SCSI controller.
- Terminal concentrator.
- CD controller.
- Serial port.
- PS/2 port.
- Parallel port.
- USB, FireWire ports (new).
Contrast single-bus design.
This is the external bus, not the internal CPU bus.
The bus is broken down into:
- Data bus.
- Address bus.
- Control bus:
- Interrupt lines.
Compared to memory, how does the CPU communicate with I/O devices?
- Ports --- The addresses an I/O device responds to.
- Interrupt --- How a device gets the CPU's attention.
- DMA channel --- Allows an I/O device to access memory directly.
- Memory-mapped I/O ports
- I/O ports in same address space as memory --- addressed same as
- Separate I/O address space
- Accessed through peek and poke.
- Control bus signal indicates which bus, memory or I/O is in use.
- Both buses can't be active simultaneously(?).
- A device's bus interface:
- I/O ports don't behave like memory words:
- They're ``active.''
- Status bits often reset when status register read.
Consider writing a buffer to a modem:
write: lb $t0, 0($t1)
poll: lw $t2, modemstatus($0)
andi $t2, $t2, 1
bnez $t2, poll
sb $t0, modemdata($0)
addi $t1, $t1, 1
addi $t3, $t3, -1
bnez $t3, write
$t0 holds the next character to write to the modem.
$t1 is the address of the next character to be written.
$t2 holds the modem's status word. Assume that bit one of the
status word is the modem buffer busy bit.
$t3 is the count of how many characters to write to the modem.
- modemstatus and modemdata are two ports associated with
- Is the modem memory-mapped?
- CPU wastes cycles polling.
- One modem transfer requires CPU to read memory and write modem.
- Interrupts are a mechanism allowing a CPU to ``disconnect'' from
active I/O devices to continue doing useful work.
- CPU much faster than most I/O devices.
- Polling wastes CPU cycles if there's other work to be done ---
Conceptually, how do interrupts work?
``Unplanned'' function calls setup by planned function calls (syscalls,
Why does the kernel initiate the I/O operation?
Components of an interrupt system:
- Interrupt request line(s). Priorities, arbitration within level,
- Interrupt acknowledge line(s).
- Interrupt handlers (service routines).
- A mechanism for indicating what device interrupted and why.
- With multiple interrupt request lines, can prioritize interrupts.
- Why do this?
- Interrupt masking --- interrupt disabling. Used for:
- Critical sections (CS 42).
- Ensuring that high-priority interrupting devices are serviced
before low-priority devices.
- Non-maskable interrupt.
If we assign one IRQ line per device, identification isn't a problem:
What if some lines are shared?
One possibility: polling.
Another: vectored interrupts.
- When interrupting device received ACK, it places interrupt
vector on bus.
- CPU uses vector as index into table of interrupt handlers.
- Privileged instruction.
- Memory protection.
- Interval timer.
- Software interrupts:
- Used to make transition from user mode to kernel mode.
Thomas P. Kelliher
Mon Oct 28 15:32:07 EST 1996