Instruction Execution

Tom Kelliher, CS26

Oct. 22, 1996

The Computer from the Programmer's Point of View

Instructions

1. Stored in memory, one or more memory words per instruction.

2. Sequentially brought into CPU for execution. (Exception: branches.)

3. Fields (op-code, operands) decoded; instruction executed.

Data

1. Stored in memory or registers.

2. Numerous addressing formats.

3. Load/store architectures require that only registers serve as operands.

How does a computer look from ``underneath the covers?''

Basic Concepts

Fundamental internal CPU registers (not seen by programmer):

1. Instruction register (IR).

2. Program counter (PC).

3. Register file (ok, this is seen by the programmer).

4. Memory address register (MAR).

5. Memory data register (MDR).

6. Temporary registers: Y, Z, and TEMP.

Two fundamental combinational circuits:

1. Arithmetic logic unit (ALU).

2. Instruction decoder.

Single bus CPU organization

• CPU bus is an internal bus, don't confuse with memory bus.

• Datapath.

• Control path.

• Single-port register file.

Instruction cycle

1. Instruction fetch IR = (PC) and PC increment PC = PC + 1. What is `` 1''?

2. Execute the instruction in IR. May require several cycles:
   1. Decode instruction.

   2. Fetch any additional instruction words.

   3. Fetch any operands.

   4. Perform operation.

   5. Store result.

Fundamental Operations

Memory Fetch

Instruction or data.

MAR = (REGx), Read         # 1 clock
WMFC                       # ? clocks
MDR = mem. data bus        # 1 clock
REGy = (MDR)               # 1 clock

• That's a lot of clocks.

• Parallelism?

• CPU bus contention.

Memory Store

MAR = (REGx)                        # 1 clock
MDR = (REGy), Assert write signal   # 1 clock
WMFC                                # ? clocks

Register Transfers

1. Storing into a register.

   Register file:

   Assert address, load signal   # 1 clock
   

   Scalar register:

   Assert load signal            # 1 clock
   

2. Reading from a register.

   Register file:

   Assert address, read enable   # 1 clock
   

   Scalar register:

   Assert read enable            # 1 clock
   

   Read enable?

   

ALU Operation Execution

Y = (REGx)
BUS = (REGy), ALU-op, Z = ALUout
REGz = Z

Adding 1?

Instruction Execution

Consider the execution of:

ADD (R3), R1

High-level execution sequence:

1. Fetch instruction.

2. Fetch memory operand.

3. Perform addition.

4. Store result in R1.

Detailed control sequencing:

1: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2: Zout, PCin, WMFC
3: MDRout, IRin
4: R3out, MARin, Read
5: R1out, Yin, WMFC
6: MDRout, Add, Zin
Zout, R1in, END

Consider the execution of:

BR ENDIF

High-level execution sequence:

1. Fetch instruction.

2. Perform addition of PC and offset.

3. Store result in PC.

Detailed control sequencing:

1: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2: Zout, PCin, WMFC
3: MDRout, IRin
4: PCout, Yin
5: Offset-field-of-IRout, Add, Zin
Zout, PCin, End

What about conditional branches?

Consider the execution of:

BZ ENDFOR

High-level execution sequence:

1. Fetch instruction.

2. Test zero condition code.

3. Conditionally:
   1. Perform addition of PC and offset.

   2. Store result in PC.

Detailed control sequencing:

1: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
2: Zout, PCin, WMFC
3: MDRout, IRin
4: PCout, Yin, if Z = 0 then End
5: Offset-field-of-IRout, Add, Zin
6: Zout, PCin, End

Hardwired Control

Executing instruction requires executing sub-instructions. How is this controlled?

Two ways of designing CPU control:

1. Hardwired control.

2. Microprogramming.

What are the inputs to the controller?

1. IR.

2. Step number.

3. Condition codes and other status flags.

Controller block diagram:

Some control equations:

PCout = T1 + ...

MARin = T1 + T4*ADD*MEMORY_OPERAND + ...

Zin = T1 + T6*ADD + T5*(BR + BZ) + ...

CPU-Memory Interaction

Asynchronous interface.

How does the CPU wait? What about the sub-cycle counter?

Refer to Fig. 3.11. For memory operations, need a circuit which:

1. Holds read/write until MFC received.

2. Disables RUN until MFC received.

Equations:

MR = Read + Readff
Readff.set = Read
Readff.reset = MFC

MW = Write + Writeff
Writeff.set = Write
Writeff.reset = MFC

Run = ~WMFC + MFC

1. Why the two flip-flops?

   1: PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin
   2: Zout, PCin, WMFC
   ...
   

2. The missing MR + MW term in RUN.