Homework 4

CS26

60 pts., due Oct. 31

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1. (10 pts.) Consider a system in which the CPU uses a control sequence similar to that in Figure 3.5 and that the CPU and memory operate synchronously.
   1. Assume that a memory operation takes the same amount of time as one internal CPU step. Rewrite the control sequence.

   2. Assume that a memory operation takes the same amount of time as two internal CPU steps. Rewrite the control sequence.

2. (10 pts.) Assume the following timing constraints:

   

   What is the minimum time that must be allowed for performing each of the following operations?

   1. Transfer data from one register to another.

   2. Increment the program counter.

   Next, consider the Add instruction that has the control sequence given in Figure 3.5. The CPU is driven by a continuously running clock signal, such that each control step is 20 ns. in duration. How long will the CPU have to wait in steps 2 and 5, assuming that a memory read operation takes 80 ns. to complete? What percentage of the time is the CPU idle during execution of this instruction?

3. (20 pts.) For each of the following instructions:
   1. Add the immediate value NUM to register R1.

   2. Add the contents of memory location NUM (direct addressing) to register R1.

   3. Add the immediate value NUM to register R1 (indexed addressing); fetch the memory location whose address is that sum and add it to register R2.

   Write the sequence of control steps for:

   1. The bus structure in Figure 3.1.

   2. The bus structure in Figure 3.13.

   Assume that each instruction consists of two words and that each word occupies one memory location. The first word specifies the operation and addressing mode, and the second word contains the constant NUM.

4. (10 pts.) Write the sequence of control steps for the instructions
   1. Add (R3), R1, Figure 3.5.

   2. The branch-on-negative instruction discussed in Section 3.2.1.

   for the bus structure in Figure 3.13.

5. (10 pts.) Write the sequence of control steps for the MIPS instructions jal and jr for the bus structure in Figure 3.13.

Extra Credit. (10 pts.) Section 3.4.1 states that the simple latches of Figure 3.3 cannot be used to implement the registers in Figure 3.13. Instead, edge-triggered or master-slave flip-flops are needed. However, would it be possible to use the latches of Figure 3.3 if a Z register were included between the output of the ALU and the C bus, similar to Figure 3.1? Justify your answer. How would this affect performance?