Tom Kelliher, CS 240

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Assignment

Background reading: pp. 353--370.

From Last Time

Completed datapath, considered control signals.

Outline

1. The control environment.

2. Setting the control signals.

3. The control unit.

4. Adding an instruction.

5. Disadvantages of the single cycle implementation.

Coming Up

A multi-cycle implementation.

The Control Environment

1. Instructions: 5 R-format(AND, OR, add, sub, slt), lw, sw, beq.

2. Instruction formats:

   

3. Summary of control signals:
   1. RegDst --- selects rt or rd field as write address.

   2. RegWrite --- write enable.

   3. ALUsrc --- selects rd2 or immediate data.

   4. PCSrc --- selects PC + 4 or branch target.

   5. MemRead --- read enable.

   6. MemWrite --- write enable.

   7. MemToReg --- selects ALU output or memory data to register file write data port.

4. Datapath block diagram:

   

Setting the Control Signals

``Playing the puppet.''

How should the control signals be set (0, 1, x) for each of the following?

1. R-format instructions.

2. lw.

3. sw.

4. beq.

The Control Unit

1. Is it combinational or sequential?

2. Why are its only inputs the opcode bits?

The control unit in place:

Adding an Instruction

How do we go about adding support for the jump instruction?

Disadvantages of the Single Cycle Implementation

Assume the following:

1. Memory read/write: 2 ns.

2. ALU and adders: 2 ns.

3. Register file read/write: 1 ns.

4. All other delays are zero (not practical).

Further assume two implementations:

1. Fixed clock rate.

2. Variable clock rate, on a per-instruction basis.

Given an instruction mix: 24% loads, 12% stores, 44% R-format, 18% branches, 2% jumps, calculate the speedup of the variable clock rate machine.

Suppose we need to add a 15 ns. instruction that is used 5% (changing R-format percentage to 39%)?

A single cycle machine cannot take advantage of differences in instruction execution times.