Sequential Logic

Tom Kelliher, CS 240

Mar. 1, 1999

Administrivia

Announcements

Homework due Wednesday. Midterm Wednesday or Friday next week?

Assignment

Read 5.1--2.

From Last Time

MRR4.

Outline

1. Definition of a finite state machine.

2. Clocks, latches, and flip-flops.

3. Design example.

Coming Up

Datapath and control design.

Finite State Machines

Model:

Clocks, Latches, and Flip-Flops

Clocks

Produced by a crystal oscillator. Features:

1. Period, frequency.

2. Falling (active) edge, fall time.

3. Rising edge, rise time.

4. set-up and hold times.

Latches

A level-sensitive clocked D latch formed from an S-R latch with gated inputs:

Operation: latch open (output follows input), latch closed (output unchanging).

What is the output for the input:

Problems with latches.

Flip-Flops

An edge-sensitive D flip-flop with a falling-edge trigger:

Trace operation.

Repeat the output waveform example.

The importance of set-up and hold times.

Bicycle Light Design Example

The product: a bicycle light which has a button and a number of LEDs. Push the button once and the LEDs shine steadily. Push again and it goes off. Push a third time and the LEDs flash on and off a few times a second. Push one more time and it goes off again.

Design steps:

1. Determination of inputs and outputs.

2. Determination of machine states.

3. Transition assignment.

4. State assignment.

5. Truth tables.

6. Implementation.

Questions along the way:

1. How many state bits?

2. The state assignment problem. In this case: simplify LED equation.

3. What to do with unused states? Don't cares; or do we care?

4. What clock frequency? Issues: design simplification, power consumption.