Memory Access, Instruction Formats, Branches and Control

Tom Kelliher, CS 240

Jan. 29, 1999

Administrivia

Announcements

Here are some Unix ``cheat sheets.'' They're in Postscript format, so I can't post them on the homepage.

SPIM handout --- one per group. See class homepage for additional copies.

Assignment

Read Sections 3.7, 3.9, 3.12--15. Summary of assigned reading from Chapter 3: everything but 3.6, 3.10--11.

From Last Time

Our conceptual datapath, memory access, arrays and pointers in assembly and C.

Outline

1. Accessing arrays and structures.

2. Instruction formats, immediate operands.

3. Branching and control structures.

Coming Up

Summary of addressing modes, survey of other instruction sets, perspectives.

Memory Addressing

1. Summary of array access:
   1. Index is a constant. A variable.

   2. Using a pointer to walk through the array. (See reverse.spim handout.)

2. Base, offset addressing, using constant offsets, is similarly useful for accessing members of structures:

   struct foo {
      int a;
      char b;
      int c;
   };
   

   

            la $s0, foo      # Assume foo is the label of the struct.
            lw $t0, 0($s0)   # load foo.a.
            lb $t0, 4($s0)   # Etc.
            lw $t0, 8($s0)
   

Instructions at the Machine Level

(Section 3.4)

1. What does a real instruction look like?

2. Consider an add instruction. What has to be there? What about a memory access instruction?

3. Bits per instruction? Variably-sized instructions? Variable field positions?

4. Design principle 3: Good design demands good compromises. One instruction width, different formats. Overlap (maintain regularity) where possible.

Instruction formats for instructions we've seen so far:

Field meanings?

Immediate Operands

1. Operand types (addressing modes) we've seen so far: registers, memory.

2. What about constants? Where have we already seen immediates? Arithmetic example:

            addi $t0, $s0, 8   # An immediate operand.
   

3. Immediate operand: found within the instruction itself.

4. Small immediates occur frequently, so...

5. Design principle 4: Make the common case fast.

6. But, how do I load a 32-bit immediate? lui followed by addi (whoops, sign extension) or ori:

            lui $s0, 0x5555
            ori $s0, $0, 0xaaaa
   

7. How does the assembler manufacture 32-bit immediates for us? Register $at.

8. Programmer conventions. ``Enhanced'' assembly language. Simplicity.

Branch and Jump Instructions

The complete set, all synthesized from beq, bne, and slt.

Branch instructions use a signed 16-bit offset field; hence they can jump instructions (not bytes) forward or instructions backwards. The jump instruction contains a 26 bit address field (the third instruction format).

b label instruction
Unconditionally branch to the instruction at the label.

beq Rsrc1, Src2, label on Equal
Conditionally branch to the instruction at the label if the contents of register Rsrc1 equals Src2.

beqz Rsrc, label on Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsrc equals 0.

bge Rsrc1, Src2, label on Greater Than Equal
bgeu Rsrc1, Src2, label on GTE Unsigned
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are greater than or equal to Src2.

bgez Rsrc, label on Greater Than Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsrc are greater than or equal to 0.

bgt Rsrc1, Src2, label on Greater Than
bgtu Rsrc1, Src2, label on Greater Than Unsigned
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are greater than Src2.

bgtz Rsrc, label on Greater Than Zero
Conditionally branch to the instruction at the label if the contents of Rsrc are greater than 0.

ble Rsrc1, Src2, label on Less Than Equal
bleu Rsrc1, Src2, label on LTE Unsigned
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are less than or equal to Src2.

blez Rsrc, label on Less Than Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsrc are less than or equal to 0.

blt Rsrc1, Src2, label on Less Than
bltu Rsrc1, Src2, label on Less Than Unsigned
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are less than Src2.

bltz Rsrc, label on Less Than Zero
Conditionally branch to the instruction at the label if the contents of Rsrc are less than 0.

bne Rsrc1, Src2, label on Not Equal
Conditionally branch to the instruction at the label if the contents of register Rsrc1 are not equal to Src2.

bnez Rsrc, label on Not Equal Zero
Conditionally branch to the instruction at the label if the contents of Rsrc are not equal to 0.

j label
Unconditionally jump to the instruction at the label.

jal label and Link
jalr Rsrc and Link Register
Unconditionally jump to the instruction at the label or whose address is in register Rsrc. Save the address of the next instruction in register 31.

jr Rsrc Register
Unconditionally jump to the instruction whose address is in register Rsrc.

Control Structures

Write MIPS code fragments corresponding to the following:

1. if (i < 12)
      ++i;
   else
      --j;
   

2. while (i > 0 && i < 200)
   {
      i = j;
      i *= i;
   }