Compilation Example, Summary of Addressing Modes, and Other Architectures

Tom Kelliher, CS 240

Feb. 3, 1999

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Assignment

Read Sections 4.1--4.3.

From Last Time

Branch instructions, control structures.

Outline

1. Compilation example.

2. Summary of addressing modes.

3. PowerPC and 80x86.

Coming Up

Number representation, addition and subtraction.

Compilation Example

I assume everyone can convert this to the equivalent while loop and compile it. If not, see me.

for (i = 1; i <= 32 ; i *= 2)
   cout << i << endl;

Summary of Addressing Modes

Effective address: location of the operand.

Possible operand locations:

1. Immediate mode: operand is in the instruction.

   

2. Register mode: operand is stored in a register whose ID is in the instruction.

   

3. Base/Offset: the memory address of the operand is the sum of a base address (stored in a register whose ID is in the instruction) and a signed immediate offset (stored in the instruction)

   

   Synthesizing other addressing modes from this.

4. PC-relative: address is the sum of the PC and a signed immediate constant.

   

5. Pseudo-Direct mode: address is the concatenation of the 4 msbs of the PC, the address field, and 00.

   

Other Instruction Sets

PowerPC: Another RISC

Basics similar to MIPS:

1. 32 registers.

2. 32-bit instructions.

3. Load-Store architecture.

Additional features:

1. Indexed addressing: address is sum of two registers.

   General applicability?

2. Update addressing: similar to base/offset addressing with the additional wrinkle of automatically incrementing the base register by sizeof(operandType) after access.

   Other strides? ALU conflicts?

3. Load/store multiple: load/store upto 32 registers in a single instruction. Useful for: register save/restore, block memory copying.

   Complexity? Can it be done with hardwired control?

4. A special loop control register, distinct from the 32 registers and accessed by a special conditional branch instruction which decrements it and then tests it ( =0, !=0).

   Useful for:

   for (i = n; i != 0; --i)
      /* code block */;
   

   Not generally useful. What it can lead to.

80x86: A CISC

MIPS was the vision of a single small group in 1985; the pieces of this architecture fit nicely together, and the whole architecture can be described succinctly. Such is not the case for the 80x86; it is the product of several independent groups who evolved the architecture over almost 20 years, adding new features to the instruction set as someone might add clothing to a packed bag.

Background:

1. Technology in the late '70s.

2. Players in the computing industry.

3. 1981: the IBM PC and Intel's changing fortunes.

   Motorola and the 68K.

Implementation history:

1. 8086 as a 16-bit extension of the 8080.

   The ``hamstrung'' 8085.

   Support for IEEE floating point.

2. 80186: The forgotten CPU.

3. 80286: 24-bit addressing, MMU, protected mode.

   The protected mode kludge.

4. 80386: 32-bit processor, real protection.

   Finally, we can run Unix on it.

5. 80486, Pentium, and Pro: Virtually no architectural changes.

6. MMX: SIMD-style small data instructions.

Basics:

1. 32-bit data and address.

2. Two-address architecture.

3. Operand combinations: register/register, register/immediate, register/memory, memory/register, memory/immediate.

4. 8 32-bit ``general purpose'' registers.

5. Several 16-bit registers: code and stack segment pointers, several data segment pointer.

6. Condition codes register. Conditions codes set as a side-effect of ALU instructions.

   Advantage: moves the compare from the branch to the ALU instruction.

   Disadvantage: superscalar, OOE.

7. Variably-sized instructions: 1 to 17 bytes. Example prefix bytes:
   1. Override default segment register.

   2. Lock the memory bus.

   3. repeat instruction until ECX clears.

Addressing modes:

1. Some instructions use postbytes to specify addressing modes.

New addressing modes:

1. Register indirect.

   Direct MIPS synthesis.

2. Base with 8- or 32-bit offset.

3. Base with scaled index

4. Base with scaled index and 8- or 32-bit offset.