Pipelining and Caches

Tom Kelliher, CS 240

Apr. 23, 1999

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Assignment

From Last Time

Pipelining.

Outline

1. Pipelining.

2. Caches.

Coming Up

More caches.

Pipelining

Hazards

1. Control hazards. Consider the following example:

   

   Solutions:

   1. Stall.

   2. Predict.

      Static prediction. Truly static. Compile-time determined.

      Dynamic prediction. Branch history tables. One-, two-bit counters.

   3. Delayed branch.

      Assumes you know branch outcome early.

      Code scheduling:

      

   Consideration: deeper pipelines.

2. Data hazards.

   Data not available when needed.

   ALU example:

   

   Fixed by forwarding.

   Memory example:

   

   How can this be fixed? Data prediction.

Superscalar Pipelines

Dynamic scheduling:

Logical vs. physical registers.

Generic structure of Pentium Pro, PowerPC 604:

Caches

The memory hierarchy:

1. Registers.

2. Main memory.

3. Disk.

4. Tape and other off-line storage.

1. The idea behind caches: provide the size of the underlying level of the hierarchy while hiding its latency.

2. Why do we have caches?

3. Where do we see them?

4. Why do they work? Locality.

5. The measure of cache effectiveness: hit rate.

   Data cache hit rates for MediaBench:

   

   Instruction cache hit rates for MediaBench:

   

   Measuring effective access time.