Multicycle Implementation State Machine, Pipelining

Tom Kelliher, CS 240

Apr. 9, 1999

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Format of the review.

Assignment

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Multicycle implementation instruction cycle.

Outline

1. Multicycle implementation state machine design.

2. Pipelining overview.

Coming Up

Pipelining.

Multicycle Implementation State Machine Design

High level view of the state machine:

Three teams:

1. Design instruction fetch/decode and jump states.

2. Design memory access states.

3. Design R-format and branch states.

Overview of Pipelining

The laundry analogy:

The five stage MIPS pipeline:

1. Instruction fetch.

2. Decode and read registers.

   The consistent placement of the source registers permits this.

3. Execute ALU operation or calculate an address.

4. Access memory.

5. Result write-back.

Comparison of Single-Cycle and Pipelined Performance

Assume:

1. Memory access is 2 ns.

2. ALU use is 2 ns.

3. Register file access is 1 ns.

Instruction class times:

Clock periods for the two implementations?

Execution example:

Note that pipelined register file reads are done during the second half of the clock cycle and writes are done during the first half. Why?

Consider the speedup:

1. Assumption: Stages are of equal length. What if they aren't?

2. Speedup is at most the number of pipeline stages.

   Do we achieve that?

   Consider the execution of 1,000 instructions and compute the actual speedup.

   What happened? The cost of the pipeline registers.

Consider:

1. How does the speedup occur?

2. Shortened instruction execution time?

3. Higher instruction bandwidth?