Finishing the Single Cycle Implementation

Tom Kelliher, CS 240

Apr. 2, 1999

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Assignment

Background reading: pp. 377--382.

Covered: Remainder of 5.4.

From Last Time

Defining the single cycle implementation's control.

Outline

1. Disadvantages.

2. Augmenting.

Coming Up

Multi-cycle implementation.

Disadvantages of the Single Cycle Implementation

Assume the following:

1. Memory read/write: 2 ns.

2. ALU and adders: 2 ns.

3. Register file read/write: 1 ns.

4. All other delays are zero (not practical).

Further assume two implementations:

1. Fixed clock rate.

2. Variable clock rate, on a per-instruction basis.

Given an instruction mix: 24% loads, 12% stores, 44% R-format, 18% branches, 2% jumps, calculate the speedup of the variable clock rate machine.

Suppose we need to add a 15 ns. instruction that is used 5% (changing R-format percentage to 39%)?

A single cycle machine cannot take advantage of differences in instruction execution times.

Augmenting the Basic CPU

Working in groups of 2--3 implement each of the following:

1. j

2. jr (R format, RS -> PC)