CMOS Transistors to Wallace Tree Multipliers: Soup to Nuts

Tom Kelliher, CS 220

Oct. 20, 1997

Announcements

Any questions on the homework?

Outline:

1. CMOS transistors: N- and P-type.

2. CMOS inverter and 2-input NOR gate.

3. Flip-flops and registers.

4. Shift-accumulate multiplier hardware.

5. Wallace tree multipliers.

Assignment

Read Intel white paper for next time.

CMOS Transistors

1. N-type transistor:
   1. Passes GND well.

   2. Degrades Vdd.

   3. Normally open switch.

2. P-type transistor:
   1. Passes Vdd well.

   2. Degrades GND.

   3. Normally closed switch.

Diagrams:

1. Terminals: gate, drain, source.

2. High capacitance on the gate.

CMOS Logic Gates

A CMOS inverter:

A CMOS 2-input NOR gate:

What determines power dissipation?

1. Switching frequency.

2. Slew rate.

Register Storage

An RS latch:

A D flip-flop:

A four-bit register:

Shift Accumulate Multipliers

Block diagram:

Wallace Tree Multipliers

Consider the partial product matrix for four-bit multiplication:

Consider the effects of carry-save adders:

Continue this. How many levels?

But, this differs from:

Tradeoff: minimize number of CSAs or minimize time.

Tradeoff: speed of Wallace tree vs. speed of shift accumulate.