Instruction Set Design

Tom Kelliher, CS 220

Nov. 14, 1997

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Handling of the final assignment (postfix calculator): completion deadline, optional milestone deadlines.

Assignment

Instruction Set Design

We descend deeper.

To execute, a program's instructions must be in memory.

What do instructions look like?

Design choices for the architect:

1. Fixed-, variable length instructions.

2. Small, large instructions.

3. Addressing modes.

4. Number and type of instructions.

5. Number of operands.

6. Size of register file. (32 for MIPS.)

Tradeoffs:

1. Silicon real estate.

2. Simplified decoding.

3. Reduced fetch bandwidth.

4. Instruction complexity.

5. Life before and after caches.

Abbreviated RISC design philosophy:

1. Instructions should be kept simple unless there is very good reason to do otherwise.

2. Simple decoding and pipelined execution are more important than program size.

RISC CPU traits:

1. Load/store; operations are register-register. Helps to reduce instruction size. Memory-memory operations are not that common given a large register file. Consider:

               .data
   a:          .word
   b:          .word
   c:          .word
   
               .text
               add a, b, c
   

   If addresses are 32-bits, how large is the add instruction?

2. The operations and addressing modes are reduced.

3. Instruction formats are simple and do not cross word boundaries.

4. RISC branches avoid pipeline penalties.

Memory Hierarchy

Programmer-visible hierarchy:

1. Registers.

2. Main memory.

3. Disk.

4. ...

Number of Operands

Consider the C code:

a = b + c;

add a, b, c      # SAL

lw $8, b($0)     # MAL  Inefficient.
lw $9, c($0)
add $8, $8, $9
sw $8, a($0)

move a, b
add a, c

load a
add b
store c

push a
push b
add
pop c

What are the advantages/disadvantages? Consider the C code:

ave = (a + b + c + d) / 4;

Sizes of instructions?

Addressing Modes

Effective address: location of the operand.

Possible operand locations:

1. Immediate mode: operand is in the instruction.

   

   This mode is used for constants.

2. Direct mode: the memory address of the operand is in the instruction.

   

   This is the model we associate with SAL.

3. Register mode: operand is stored in a register whose ID is in the instruction.

   

   Similar to direct mode, but faster and a far smaller ``memory.''

4. Register direct mode: the memory address of the operand is stored in a register whose ID is in the instruction.

   

   The register is a pointer.

5. Base Displacement: the memory address of the operand is the sum of a base address (stored in a register whose ID is in the instruction) and an immediate displacement (stored in the instruction)

   

   Displacements are signed.

   Array, struct access. Not so much array.

   Branch instructions use PC-relative addressing, which is similar to Base displacement:

   1. PC is base.

   2. Displacement is stored as a signed immediate in the instruction.

   3. When branch taken, computed address is stored into PC.