CMOS Transistors to Wallace Tree Multipliers: Soup to Nuts

Tom Kelliher, CS 220

Nov. 7, 1997

Assignment

Read Chapter 7. Homework assignment due Nov. 14, available on class home page.

Register Storage

An RS latch:

A D flip-flop:

A four-bit register:

Block diagram of a register file:

1. ALU reads two operands and writes one.

2. Relationship between number of address lines, number of registers?

3. WE - write enable.

4. Cl - clock.

More detail of the register file:

1. Decoder: n inputs, outputs. The inputs, interpreted as a binary number, specify which one of the output lines to drive high (logic 1). All other output lines stay low (logic 0).

2. Multiplexer: A -to-1 switch. The n address inputs specifies which of the data inputs to send to the output. To switch 32 32-bit lines, 32 32-to-1 muxes are used, with their address inputs all tied together. (Demonstrate switching 4 4-bit registers.)

3. A RAM behaves similarly, but the implementation is not the same.

4. Note that the decoder output is gated by the WE signal, preventing spurious register writes.

Shift Accumulate Multipliers

Block diagram:

Wallace Tree Multipliers

Consider the partial product matrix for four-bit multiplication:

Consider the effects of carry-save adders:

Continue this. How many levels?

But, this differs from:

Tradeoff: minimize number of CSAs or minimize time.

Tradeoff: speed of Wallace tree vs. speed of shift accumulate.

Piecing It All Together

A model of a simple, non-pipelined datapath:

The MIPS instruction formats:

1. The fields and decoding.

2. Immediates:
   1. A 32-bit move?

   2. Two immediate values needed for conditional branch with register compared to immediate?

3. Aren't 32-bits needed for a jump instruction?

Walk through:

1. An add.

2. A beq.