CMOS Transistors to Wallace Tree Multipliers: Soup to Nuts

Tom Kelliher, CS 220

Oct. 20, 1997

Assignment

Read Chapter 7.

CMOS Transistors

1. N-type transistor:
   1. Passes GND well.

   2. Degrades Vdd.

   3. Normally open switch.

2. P-type transistor:
   1. Passes Vdd well.

   2. Degrades GND.

   3. Normally closed switch.

Diagrams:

1. Terminals: gate, drain, source.

2. High capacitance on the gate.

CMOS Logic Gates

A CMOS inverter:

A CMOS 2-input NOR gate:

What determines power dissipation?

1. Switching frequency.

2. Slew rate.

Register Storage

An RS latch:

A D flip-flop:

A four-bit register:

Shift Accumulate Multipliers

Block diagram:

Wallace Tree Multipliers

Consider the partial product matrix for four-bit multiplication:

Consider the effects of carry-save adders:

Continue this. How many levels?

But, this differs from:

Tradeoff: minimize number of CSAs or minimize time.

Tradeoff: speed of Wallace tree vs. speed of shift accumulate.

Piecing It All Together

A model of a simple, non-pipelined datapath:

The MIPS instruction formats:

1. The fields and decoding.

2. Immediates:
   1. A 32-bit move?

   2. Two immediate values needed for conditional branch with register compared to immediate?

3. Aren't 32-bits needed for a jump instruction?

Walk through:

1. An add.

2. A beq.