---------------------------------------------------------------------------
-- system
--
-- This is the top level module for the updown counter assignment.
---------------------------------------------------------------------------
-- Implementing this module requires adding signal declarations, component
-- instantiations, and a bit of dataflow VHDL.  You must not modify
-- system's port statement, the pin constraints, or the component
-- declarations.
---------------------------------------------------------------------------
-- IMPORTANT NOTE ABOUT BUILDING THIS LOGIC IN ISE
--
-- Before building this logic in ISE:
--  1.  In Project Navigator, right-click on "Generate Programming File"
--      (in the Process View Tab) and select "Process Properties"
--  2.  Click the "Startup Options" tab
--  3.  Set the "FPGA Start-Up Clock" to "JTAG Clock"
---------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity system is

  port (   -- DO NOT MODIFY!!!
    clk, upDown, enable, reset : in std_logic;
    seg                          : out std_logic_vector(6 downto 0);
    dp                           : out std_logic;
    an                           : out std_logic_vector(3 downto 0)
    );
  
end system;

architecture Structural of system is

---------------------------------------------------------------------------
-- Pin Constraints
-- DO NOT MODIFY!!!
---------------------------------------------------------------------------

  attribute LOC : string;
  attribute LOC of clk : signal is "B8";
  attribute LOC of upDown : signal is "K18";  -- SW2
  attribute LOC of enable : signal is "H18";  -- SW1
  attribute LOC of reset : signal is "G18";   -- SW0

  -- The attributes below are for the four digit seven segment
  -- display.
  attribute LOC of seg : signal is "L18 F18 D17 D16 G14 J17 H14";
  attribute LOC of dp : signal is "C17";
  attribute LOC of an : signal is "F15 C18 H17 F17";

---------------------------------------------------------------------------
-- Component Declarations
-- DO NOT MODIFY!!!
---------------------------------------------------------------------------

  component SwitchDebouncer is
    generic (CLK_FREQ       : positive;
             NUM_SWITCHES   : positive);
    port (   clk            : in  std_logic;
             reset          : in  std_logic;
             switchesIn     : in  std_logic_vector(NUM_SWITCHES-1 downto 0);
             switchesOut    : out std_logic_vector(NUM_SWITCHES-1 downto 0));
  end component;

  component upDownCounter is
    
    port (
      enable, up_down, clk, reset : in  std_logic;
      count                         : out std_logic_vector (3 downto 0);
      wrap                          : out std_logic
      );

  end component;

  component divCounter is
    
    port (
      clk, reset : in  std_logic;
      ovfl         : out std_logic);

  end component;

  component SimpleSevenSegDriver is
    port (  clk            : in  std_logic;
            reset          : in  std_logic;

            digit0         : in  std_logic_vector(3 downto 0);
            digit1         : in  std_logic_vector(3 downto 0);
            digit2         : in  std_logic_vector(3 downto 0);
            digit3         : in  std_logic_vector(3 downto 0);

            dpIn           : in  std_logic_vector(3 downto 0);

            seg            : out std_logic_vector(6 downto 0);
            dp             : out std_logic;
            an             : out std_logic_vector(3 downto 0));
  end component;

---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------

---------------------------------------------------------------------------
-- Module Implementation
--
-- In addition to component instantiation, a bit of dataflow VHDL will be
-- necessary.
---------------------------------------------------------------------------

begin

end Structural;