---------------------------------------------------------------------------
-- SimpleSevenSegDriver
--
-- This VHDL module was obtained from
-- http://www.labbookpages.co.uk/electronics/debounce.html.  A few
-- modifications have been made.
--
-- Nothing in this module should be modified.
---------------------------------------------------------------------------
-- This VHDL module is a driver for the Nexys 2 board's four digit
-- seven segment display.  The driver is designed to display the
-- hexadecimal character set.  Hence, four bits are needed per digit.  The
-- display's four digits are controlled by the digit0 through digit3 input
-- vectors.  digit0 is the least significant digit and digit3 is the most
-- significant digit.  The display digits' decimal points are controlled
-- by dpIn.  The bits of dpIn are active low.

-- The reset signal is active high and synchronous.  When reset is
-- asserted digit0 will display a "0".  The remaining digits will not
-- display anything.
--
-- Due to the chip design of the display, the digit inputs are multiplexed
-- over seven pins using the an pins.  This is handled automatically by
-- the driver.
--
-- For the Nexys 2 board, the following pin constraints must be used:
--    attribute LOC of seg : signal is "L18 F18 D17 D16 G14 J17 H14";
--    attribute LOC of dp : signal is "C17";
--    attribute LOC of an : signal is "F15 C18 H17 F17";
-- Note that if this module is used as a component in a larger design,
-- then these pin contraints must be used with the top level module's
-- port outputs.
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SimpleSevenSegDriver is
  port ( clk            : in  std_logic;
         reset          : in  std_logic;

         digit0         : in  std_logic_vector(3 downto 0);
         digit1         : in  std_logic_vector(3 downto 0);
         digit2         : in  std_logic_vector(3 downto 0);
         digit3         : in  std_logic_vector(3 downto 0);

         dpIn           : in  std_logic_vector(3 downto 0);

         seg            : out std_logic_vector(6 downto 0);
         dp             : out std_logic;
         an             : out std_logic_vector(3 downto 0));
end SimpleSevenSegDriver;

architecture Arch of SimpleSevenSegDriver is

  signal anode    : std_logic_vector(3 downto 0) := "1110";

begin

  an <= anode;

  process (clk)
    variable bcd     : std_logic_vector(3 downto 0);
    variable counter : unsigned(7 downto 0);
  begin
    if (clk'event and clk='1') then
      if (reset='1') then
        bcd := (others => '0');
        counter := (others => '0');
        seg <= "0000001";
        anode <= b"1110";

      else
        if (counter=b"0000_0000") then
          anode <= anode(2 downto 0) & anode(3);
        end if;

        counter := counter + 1;

        case anode is
          when "1110" => bcd  := digit0;
                         dp      <= dpIn(0);
          when "1101" => bcd  := digit1;
                         dp      <= dpIn(1);
          when "1011" => bcd  := digit2;
                         dp      <= dpIn(2);
          when others => bcd  := digit3;
                         dp      <= dpIn(3);
        end case;

        -- Display Segments: A B C D E F G
        case bcd is
          when "0000" => seg <= "0000001";   -- 0
          when "0001" => seg <= "1001111";   -- 1
          when "0010" => seg <= "0010010";   -- 2
          when "0011" => seg <= "0000110";   -- 3
          when "0100" => seg <= "1001100";   -- 4
          when "0101" => seg <= "0100100";   -- 5
          when "0110" => seg <= "0100000";   -- 6
          when "0111" => seg <= "0001111";   -- 7
          when "1000" => seg <= "0000000";   -- 8
          when "1001" => seg <= "0000100";   -- 9
          when "1010" => seg <= "0001000";   -- A
          when "1011" => seg <= "1100000";   -- B
          when "1100" => seg <= "0110001";   -- C
          when "1101" => seg <= "1000010";   -- D
          when "1110" => seg <= "0110000";   -- E
          when others => seg <= "0111000";   -- F
        end case;
      end if;
    end if;
  end process;

end Arch;