---------------------------------------------------------------------------
-- comp2.vhd
---------------------------------------------------------------------------
-- Use this VHDL source file as the starting point for you VHDL
-- implementation of the 2's complement problem.
--
-- You should NOT change the entity statement.
--
-- The system for this problem consists of this file, the comp2System.vhd
-- file, and the eppInterface.vhd file.  Comp2System is the top-level
-- module for this project.
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;


entity comp2 is

  port (
    x, reset, clk : in  std_logic;
    z             : out std_logic);

end comp2;


architecture state_machine of comp2 is

begin

end state_machine;