-- Dataflow VHDL for a one-bit full adder. library ieee; use ieee.std_logic_1164.all; entity fa is port ( a, b, c_i : in std_logic; c_o, s : out std_logic ); end fa; architecture dataflow of fa is begin s <= a xor b xor c_i; c_o <= (a and b) or (a and c_i) or (b and c_i); end dataflow;