Building a Datapath

Tom Kelliher, CS 240

Mar. 13, 2002

Administrivia

Announcements

Homework due Wednesday. Exam Friday.

Assignment

Read Section 5.3.

From Last Time

Multiplication.

Outline

1. Overview of the implementation.

2. Parts of the implementation.

Coming Up

Merging the parts: a simple implementation.

Overview of the MIPS Implementation

The general instruction cycle:

1. Instruction fetch.

2. Instruction decode.

3. Register fetch.

4. Operate.

5. Register store or memory operation.

A high level view of the implementation, in view of the instruction cycle:

1. Datapath only.

2. Is everything we need for our instructions here?

Building a Datapath

Strategy: Look at the major datapath components needed to execute each class of instructions.

Hardware needed:

1. Individual registers (PC).

2. Register file.

3. Memory (data memory).

4. ALU.

5. Sign extend, shift?

Instruction Fetch

Common to all instruction formats.

Requirements:

1. Store program.

2. Remember which instruction is to be executed next.

3. Fetch next instruction. (And store.)

Elements:

1. A register for the PC.

2. A memory for the program.

3. An adder to update the PC.

Organization:

The adder is a hardwired ALU.

R-Format

Requirements:

1. Fetch two register operands.

2. Operate.

3. Store result back into a register.

Elements:

1. A 32 word by 32 bit register file with two read ports and a write port (read B-25--B-26).

2. An ALU.

Organization:

Control signals: Write, ALU Control, Zero.

I-Format

Requirements:

1. Immediate mode arithmetic-logic instructions:
   1. Replace one source register with sign-extended immediate value.

2. Memory reference instructions:
   1. Add base register and sign-extended offset.

   2. Transfer data

3. Branch instructions:
   1. Compare register values.

   2. Conditionally update PC with PC + 4 + sign-extended, shifted offset.

Elements: R-format elements plus:

1. Substitution of a register source value with the immediate value.

2. A data memory.

3. A mechanism for loading a branch target address into the PC.

Organizations:

Immediate mode arithmetic-logic instructions:

Memory reference instructions:

Branch instructions: