Tom Kelliher, CS 240
Apr. 15, 2002
Read 6.3.
Overview of pipelining.
Pipelined control.
A pipelined datapath:

Consider four instructions: R-mode, a branch, LW, SW.
Observations:
Example: unified L1 cache/memory.

Solutions:
Static prediction. Truly static. Compile-time determined.
Dynamic prediction. Branch history tables. One-, two-bit counters.
Assumes you know branch outcome early.
Code scheduling:

Consideration: deeper pipelines.
Data not available when needed.
ALU example:

Fixed by forwarding.
Memory example:

How can this be fixed?
Let's follow a lw. What's going on during each clock cycle?


