The Memory Hierarchy

Tom Kelliher, CS 240

Mar. 27, 2000

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Assignment

Read 7.1--7.2.

From Last Time

Crusoe.

Outline

1. Introduction, terminology.

2. Basics of caches.

Coming Up

Caches: direct mapped, set associative, fully associative.

Introduction

1. Memory technology:
   1. SRAM. (20 ns., 256 KB synch. pipeline burst L2 cache, $525)

      Four to six transistors/bit. Faster access.

   2. DRAM. (64 MB PC100 ECC SDRAM, $50).

      One transistor/bit. Slower access. Refresh. Improvements: page mode. synchronous mode.

      How is a DRAM addressed: RAS, CAS?

      Parity, ECC.

   3. Magnetic disk. (16.8 GB, 7200 RPM IDE disk, $129)

      Parts of a disk: heads, spindle, platters, cylinders, tracks, sectors. The ``flying'' head.

      Addressing a sector: CHS, LBA.

      Components of a disk access: seek, rotational latency, sector access.

      Caches on disks.

2. Memory is a hierarchy: registers, cache, main memory, disk, tape.

   How does cost, speed, size vary over this hierarchy?

3. Key idea: Trick the processor into believing it has a large, fast memory. How can we accomplish this?

4. Principle of locality allows us to keep a subset of the memory space high in the hierarchy, where it fits and where access is fast. Because, a program uses just a small part of its address space at any instant.

   (You know you need more RAM when you hear your disks seeking a lot.)

   Two types of locality:

   1. Temporal locality.

   2. Spatial locality.

   We concentrate upon two points in the memory hierarchy: cache/main memory and main memory/disk:

   1. Cache/main memory: handled by the hardware. Not a part of the system architecture.

   2. Main memory/disk: handled by the OS. The virtual memory system.

5. Terminology: block, hit, hit rate, miss, miss penalty. (Define.)

   Block sizes for caches, disks.

Basics of Caches

1. Think of memory being partitioned into blocks, called lines when in the cache.

2. Think of the cache as being partitioned into lines and lines being partitioned into sets, where the set size can be:
   1. One line: direct mapped cache.

   2. All lines: fully associative cache.

   3. Between the first two, but a power of two.

   A given memory block is always loaded into the same set.

   With a direct mapped cache, two blocks in the same set can't be in cache at the same time.

3. Think of a memory address being partitioned into two pieces: the tag and the set selector (low order bits)

4. Basic parameters of cache design: size of cache (may include data, tag, valid bit), size of line, set size.