Code Scheduling on a Superscalar Pipeline, OOE Execution

Tom Kelliher, CS 240

Feb. 23, 2000

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Collect assignment 1.

Assignment

From Last Time

Code scheduling.

Outline

1. Code scheduling examples.

2. OOE: scoreboarding, Tomasulo, committing instructions.

Coming Up

PSU TEE.

In-Order Execute Pipeline

Pentium Example: basically one integer and one floating point unit; no instruction alignment requirements.

Instruction Scheduling Example

Suppose you don't have hardware integer multiply. Then you'll need something like:

a = mutiplicand;              /* $s1 */
b = multiplier;               /* $s2 */
product = 0;                  /* $s3 */
bit = 1;                      /* $s4 */

for (i = 0; i < 32; ++i)      /* $s5 */
{
   if (b & bit)
      prod += a;

   bit += bit;
   a += a;
}

top:     and $t0, $s2, $s4
         beq $t0, $0, skip
         addu $s3, $s3, $s1   /* addu1 */
skip:    addu $s1, $s1, $s1   /* addu2 */   
         addu $s4, $s4, $s4   /* addu3 */
         addi $s5, $s5, -1
         bne $s5, $0, top

Suppose we assume we can perform two R-format instructions simultaneously:

Assumptions:

1. Branch target must be double word-aligned.

2. The instruction paired with a branch is always executed. (Text appears to assume this. In a sense, this is the delay slot here.)

3. The instruction pair slot following a branch instruction pair is not a delay slot. (Not a good assumption.)

Let's unroll once:

Out of Order Superscalar Pipelines

Two types we'll examine:

1. Scoreboarding: CDC 6600, 1964, first pipelined supercomputer, load/store, 16 functional units: 4 fp, 5 load/store, 7 integer.

2. Tomasulo's algorithm: IBM 360/91, 1967, the supercomputer that made the Justice Department look at IBM. 360 architecture had only 4 fp registers, long memory access, long fp delay. Tomasulo's algorithm was designed to overcome this.

   This lay, forgotten, for over 20 years...

Scoreboarding

1. Uses only ISA registers.

2. Instructions issue in order to FUs.

3. Instructions execute out of order.

4. The scoreboard is hardware which determines when an FU can begin: source register values ready and complete: destination register value no longer needed.

5. Does not eliminate WAR or WAW dependencies. So, what good is it?

Tomasulo's Algorithm

1. Uses reservation stations (physical registers).

2. Instructions issue in order to reservation stations.

3. Instructions execute out of order.

Example FUs:

1. Integer.

2. FP.

3. Load/Store. Write buffers.

4. Branch.

Committing Instructions

1. Instructions must commit in order, otherwise imprecise interrupts.

2. The reorder buffer: instructions placed in order there.

3. An instruction cannot commit until:
   1. Branches resolve.

   2. Instructions before it commit.

   3. The value it produces is ready.

4. Multiple commits per cycle.