Paging, Virtual Memory
Tom Kelliher, CS 240
Apr. 14, 2000
Amanda's assignment?
Read 7.5.
Virtual addresses, paging.
- Virtual memory, paging.
Virtual memory.
Paging hardware:

Design issues:
- Page size:
- Internal fragmentation.
- Maximizing I/O transfer rate.
- I/O --- process passes logical address to kernel.
- Implementation of the page table.
- Small register file.
- Array in memory.
- Issues for memory implementation:
- Page table must be in contiguous memory.
- Page table base register.
- ``Logical memory access'' requires two physical accesses.
- Translation look-aside buffer.
- TLB entries contain: Page number, frame number pairs.
- Issue: Context switches.
- Only a few entries needed.

- Problem: huge page tables. How did this happen?
- Solutions:
- Valid/invalid bit.
- Page table limit register.
- Multi-level paging.
- Is it possible for a process to access an arbitrary memory location?
- Using valid bit to introduce ``holes'' into logical address space.
- What can be shared?
- Read-only pages.
- Page alignment --- segment the logical address space.
- Page de-allocation.
- Virtual memory --- what is it?

- What are the advantages?
- A program's logical address space can be larger than physical
memory.
- Degree of multiprogramming can be increased (40 pages of memory;
allocate only 5 pages to processes with spaces of 10 pages).
- Less I/O needed to load/swap a process.
- Demand paging.
- Why does it work?
- A lot of code is rarely run (error-handling routines).
- Oversizing of data structures.
- Locality of reference:
- Spatial.
- Temporal.
What we'll consider:
- System support.
- Page fault sequence.
- Replacement policies.
- Placement (allocation) policies.
- Kernel support.
- MMU support.
- CPU support.
- Page fault handler.
- Page placement policies.
- Page replacement policies.
Thomas P. Kelliher
Fri Apr 14 10:10:22 EDT 2000
Tom Kelliher