Caches

Tom Kelliher, CS 240

Apr. 5, 2000

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Assignment

Homework, due 4/12.

From Last Time

Write-through, write-back caches.

Snooping caches.

Exploiting spatial locality.

Outline

1. Multiple words/block cache.

2. Memory system design.

3. Measuring cache performance.

Coming Up

Associativity.

Direct Mapped Caches

Second Cache

Let's design another cache. Parameters:

1. Direct mapped.

2. Block size is four words. Why would we want a larger block size? (Exploit spatial locality)

   Consider the hit rate when fetching eight words consecutively with block sizes of one and four words.

   To a point, increasing block size increases the hit rate. At what point does this break down?

3. 4K blocks.

4. 32 bit memory space.

Questions:

1. How many bits/block? Total size of the cache?

2. Size of the data portion of the cache, in bytes? (This is the number you see quoted.)

Organization of the cache:

Consider:

1. Why would we want a larger block size? (Exploit spatial locality)

   Consider the hit rate when fetching eight words consecutively with block sizes of one and four words.

2. To a point, increasing block size increases the hit rate. At what point does this break down? Why? (Fewer blocks.)

   Also, the miss penalty time will increase because of larger memory transfers.

3. How can a load instruction result in a memory write? How can a store instruction result in a memory read?

Memory System Design

Three memory organizations:

What is interleaving and its history?

Memory access delays:

1. One cycle to send an address. To access a block, we send just one address.

2. 15 cycles to allow DRAM operation to complete.

3. One cycle to transmit data.

Compute the bytes/cycle for each organization for four word blocks.

Points to consider:

1. The real point of interleaving is that we now have several independent memories.

   So we can perform several writes simultaneously, assuming we can write single words. This increases our write bandwidth, leading to fewer stalls.

2. But, DRAM sizes keep increasing, decreasing the number of banks for a given memory size.

Measuring Cache Performance

Two Equations:

Example One

Consider a gcc run:

1. I-cache miss rate is 2%. D-cache miss rate is 4%.

2. CPI is 2, assuming no memory stalls.

3. Miss penalty is 40 cycles.

4. 36% of instructions are load or store.

Example Two

Suppose we improve the pipeline so that the CPI is now 1. Repeat. (2.36.)

Example Three

Compare the speed-up of a real machine with a doubled clock rate against the original real machine. Assume the memory system has the same cycle time. (1.41.)