--------------------------------------------------------------------------- -- upDownCounter -- -- This module implements a one digit decimal counter, capable of counting -- up or down. -- -- The counter should only increment/decrement when the enable input is -- high. If up_down is low, the counter decrements; otherwise, the -- counter increments. The counter counts modulo 10. The counter's BCD -- output is output via the count vector. The counter's wrap output -- should be high when the counter is about to make the 0 -> 9 or 9 -> 0 -- transition. Note that this implies that the enable input is high and -- that the reset input is low. -- -- The reset signal is asynchronous and active high. Reset has priority -- over all other control signals. --------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity upDownCounter is port ( enable, up_down, clk, reset : in std_logic; count : out std_logic_vector (3 downto 0); wrap : out std_logic ); end upDownCounter; architecture behavioral of upDownCounter is begin end behavioral;