---------------------------------------------------------------------------- -- electronicLockSystem.vhd -- Top-level VHDL module for the electronic -- lock problem. -- -- Nothing in this module should be modified. ---------------------------------------------------------------------------- -- IMPORTANT NOTE ABOUT BUILDING THIS LOGIC IN ISE -- -- Before building the electronicLockSystem logic in ISE: -- 1. In Project Navigator, right-click on "Generate Programming File" -- (in the Process View Tab) and select "Process Properties" -- 2. Click the "Startup Options" tab -- 3. Set the "FPGA Start-Up Clock" to "JTAG Clock" ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity electronicLockSystem is port ( clk : in std_logic; t : in std_logic; k : in std_logic; lock : in std_logic; unlock : in std_logic; locked : out std_logic; unlocked : out std_logic; ignoringInputs : out std_logic); end electronicLockSystem; architecture structural of electronicLockSystem is --------------------------------------------------------------------------- -- Pin Constraints -- DO NOT MODIFY!!! --------------------------------------------------------------------------- attribute LOC : string; attribute LOC of clk : signal is "B8"; attribute LOC of t : signal is "H13"; -- BTN3 attribute LOC of k : signal is "E18"; -- BTN2 attribute LOC of lock : signal is "D18"; -- BTN1 attribute LOC of unlock : signal is "B18"; -- BTN0 attribute LOC of locked : signal is "K15"; -- LD2 attribute LOC of unlocked : signal is "J15"; -- LD1 attribute LOC of ignoringInputs : signal is "J14"; -- LD0 --------------------------------------------------------------------------- -- Component Declarations --------------------------------------------------------------------------- component electronicLock is port ( clk : in std_logic; t : in std_logic; k : in std_logic; lock : in std_logic; unlock : in std_logic; locked : out std_logic; unlocked : out std_logic; ignoringInputs : out std_logic); end component; component SwitchDebouncerTrans is generic (CLK_FREQ : positive; NUM_SWITCHES : positive); port ( clk : in std_logic; reset : in std_logic; switchesIn : in std_logic_vector(NUM_SWITCHES-1 downto 0); switchesOut : out std_logic_vector(NUM_SWITCHES-1 downto 0)); end component; --------------------------------------------------------------------------- -- Signal declarations --------------------------------------------------------------------------- signal rawSwitches : std_logic_vector(3 downto 0); signal dbSwitches : std_logic_vector(3 downto 0); signal dbT, dbK, dbLock, dbUnlock : std_logic; --------------------------------------------------------------------------- -- Module Implementation --------------------------------------------------------------------------- begin rawSwitches <= t & k & lock & unlock; dbT <= dbSwitches(3); dbK <= dbSwitches(2); dbLock <= dbSwitches(1); dbUnlock <= dbSwitches(0); elock : electronicLock port map ( clk => clk, t => dbT, k => dbK, lock => dbLock, unlock => dbUnlock, locked => locked, unlocked => unlocked, ignoringInputs => ignoringInputs); swdb : SwitchDebouncerTrans generic map ( CLK_FREQ => 50000000, NUM_SWITCHES => 4) port map ( clk => clk, reset => '0', switchesIn => rawSwitches, switchesOut => dbSwitches); end structural;