---------------------------------------------------------------------------
-- divCounter
--
-- This module's ovfl output should go high for exactly one clock period
-- each second.
--
-- The Nexys 2 board's clock frequency is 50 MHz.  Therefore this counter
-- should count modulo 50,000,000, with the ovfl signal going high when
-- the count reaches 49,999,999.
--
-- The reset signal is asynchronous and active high.
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divCounter is
  
  port (
    clk, reset : in  std_logic;
    ovfl         : out std_logic);

end divCounter;

architecture behavioral of divCounter is

begin
  
end behavioral;