----------------------------------------------------------------------------
-- comp2System.vhd -- Top-level VHDL module for 2's complement assignment.
--
-- Nothing in this module should be modified.
----------------------------------------------------------------------------
-- IMPORTANT NOTE ABOUT BUILDING THIS LOGIC IN ISE
--
-- Before building the comp2System logic in ISE:
--  1.  In Project Navigator, right-click on "Synthesize-XST"
--      (in the Process View Tab) and select "Process Properties"
--  2.  Click the "HDL Options" tab
--  3.  Set the "FSM Encoding Algorithm" to "None"
--  4.  In Project Navigator, right-click on "Generate Programming File"
--      (in the Process View Tab) and select "Process Properties"
--  5.  Click the "Startup Options" tab
--  6.  Set the "FPGA Start-Up Clock" to "JTAG Clock"
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp2System is
    Port (
        mclk    : in std_logic;
        pdb     : inout std_logic_vector(7 downto 0);
        astb    : in std_logic;
        dstb    : in std_logic;
        pwr     : in std_logic;
        pwait   : out std_logic;
        rgan    : out std_logic_vector(3 downto 0)
    );
end comp2System;

architecture Structural of comp2System is

------------------------------------------------------------------------
-- Pin Constraints
-- DO NOT MODIFY!!!
------------------------------------------------------------------------

  attribute LOC : string;
  attribute PULLUP : string;

  -- The following pin constraints are for the USB interface.
  attribute LOC of mclk : signal is "B8";
  attribute LOC of pdb : signal is "R10 P10 R11 N11 T12 P13 R13 R14";
  attribute LOC of astb : signal is "V14";
  attribute LOC of dstb : signal is "U14";
  attribute LOC of pwr : signal is "V16";
  attribute LOC of pwait : signal is "N9";

  -- The following pin constraints are intended to ensure that the
  -- seven segment displays are off.  I'm not sure that this is
  -- necessary, but it doesn't seem to hurt.
  attribute LOC of rgan : signal is "F15 C18 H17 F17";
  attribute PULLUP of rgan : signal is "TRUE TRUE TRUE TRUE";

------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------

  component eppInterface is
    Port (
        mclk    : in std_logic;
        pdb     : inout std_logic_vector(7 downto 0);
        astb    : in std_logic;
        dstb    : in std_logic;
        pwr     : in std_logic;
        pwait   : out std_logic;
        rgan    : out std_logic_vector(3 downto 0);
        C2Z     : in std_logic;
        C2X     : out std_logic;
        C2CLK   : out std_logic;
        C2RESET : out std_logic
    );
end component;

component comp2 is
    Port (
        x     : in std_logic;
        reset : in std_logic;
        clk   : in std_logic;
        z     : out std_logic
    );
end component;

------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------

signal x : std_logic;
signal z : std_logic;
signal clk : std_logic;
signal reset : std_logic;

------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------

begin

  EPP: eppInterface
    port map (
      mclk    => mclk,
      pdb     => pdb,
      astb    => astb,
      dstb    => dstb,
      pwr     => pwr,
      pwait   => pwait,
      rgan    => rgan,
      C2Z     => z,
      C2X     => x,
      C2CLK   => clk,
      C2RESET => reset);

  UUT: comp2
    port map (
      x     => x,
      reset => reset,
      clk   => clk,
      z     => z);
    
end Structural;