/***********************************************************************
 * comp2.cpp
 *
 * Test driver for 6-35 on pg. 308 of Mano & Kime.
 *
 * This code assumes the following:
 *
 *    Signal         Parallel Port Pin
 *    ------         -----------------
 *    CLK            D0
 *    X              D2
 *    Y              D3
 *    Z              S3
 *
 * Optionally, an active low RESET can be used at D1 on the parallel
 * port.
 ***********************************************************************/

#include <stdio.h>
#include "pport.h"


/* Bit masks for the FPGA inputs.  Note that RESET is active low, so
 * it will *ordinarily* be set.
 */

#define CLOCK 0x1
#define RESET 0x2
#define X 0x4
#define Y 0x8


/* Function prototypes. */

int fpga(int in);


/***********************************************************************
 * main()
 ***********************************************************************/

int main()
{
   int val;   /* The input value we'll be complementing. */

   printf("Enter the end-of-file character (ctrl-z) to exit.\n");

   /* Raise Y and give a clock pulse to initialize the state.
    * machine.
    */
   writeDataReg(Y | RESET);
   writeDataReg(CLOCK | Y | RESET);
   writeDataReg(Y | RESET);

   while (1)
   {
      printf ("\nEnter a signed integer: ");
      if (scanf("%d", &val) == EOF)
         break;

      printf("Entered value:                      %d\n", val);
      printf("FPGA-computed 2's complement value: %d\n", fpga(val));
   }

   printf("\n\nExiting.\n");

   return 0;
}


/***********************************************************************
 * int fpga(int in)
 *
 *    in : a signed 32-bit number.
 *
 *    returns: (hopefully) the 2s complement of in.  The work is done
 *    by the VHDL program on the FPGA board.
 ***********************************************************************/

int fpga(int in)
{
   int out = 0;   /* The complemented value we're constructing. */
   int bit = 1;   /* The current bit position of out we're working on. */
   int i;

   for (i = 0; i < 32; ++i)
   {
      /* CLOCK is low.  Send over the current bit of in.  If this is the
       * last bit of in, raise Y to get ready for the next input.
       */
      writeDataReg(((in & 0x1) ? X : 0)
                   | ((i == 31) ? Y : 0)
                   | RESET);

      /* The output should be ready now.  Read it and update out. */
      if (readStatusReg() & 0x1)
         out |= bit;

      /* Pulse CLOCK. */
      writeDataReg(CLOCK
                   | ((in & 0x1) ? X : 0)
                   | ((i == 31) ? Y : 0)
                   | RESET);
      writeDataReg(((in & 0x1) ? X : 0)
                   | ((i == 31) ? Y : 0)
                   | RESET);

      /* Shift in one bit right to access the next bit to be
       * complemented and shift bit one bit left.
       */
      in >>= 1;
      bit <<= 1;
   }

   return out;
}