Macro Architectural Trends; IC Fabrication

Tom Kelliher, CS 220

Sept. 11, 2009

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Assignment

Read 2.1-2.6.

First homework will be posted later today.

From Last Time

Performance.

Outline

Coming Up

Macro Architectural Trends

The power equation:

\begin{displaymath} {\rm Power} = {\rm Capacitance} \times {\rm Voltage}^2 \times {\rm Clock\ Rate} \end{displaymath}

  1. Capacitance: What is it, what contributes to it? Trends.

  2. Voltage: Trends and limits.

  3. Clock Rate: Trends.

``Sea change'' from uniprocessing to multiprocessing:

  1. Easy to increase uniprocessor performance if you can constantly overclock.

  2. Explicit parallelism -- the ``third rail'' of CA.

  3. Explicit parallelism -- we've been here before: supercomputers.

  4. What's the future of this trend?

How did we get here?

  1. The ``Clock'' wars.

  2. Implicit parallelism -- ILP:
    1. Deep pipelining, branch prediction, speculative execution.

    2. Trace caches.

    3. Multiple issue.

    4. Register renaming, out of order execution.

    The cost of high clock rates and all this complexity: power.

  3. Heat dissipation in commodity microprocessors.

We've been here before: the CISC/RISC crossroads

  1. CA was more art than science -- few quantitative studies.

  2. Trends:
    1. Move software functionality into hardware -- more and more HLL support.

      More ``powerful'' instructions are not always faster -- the 11/780 INDEX instruction.

    2. Historically, memory bandwidth had to be conserved.

      Achieved by:

      1. Dense, complex instruction sets.

      2. Microcode techniques.

      3. Feature creep.

  3. Consequences:
    1. Faster memory hierarchy.

    2. ``Irrational'' implementations.

    3. Increased design time.

    4. Increased design errors.

  4. Faster memory and VLSI technology broke the complexity trend.

Moral of the story: re-evaluate your assumptions on a regular basis.

(Additional background: See ``The Case for the Reduced Instruction Set Computer'' on the web site.

IC Fabrication

A little more background...

  1. Die, package details.

    \begin{figure}\centering\includegraphics[]{Figures/chip.eps}\end{figure}

    Core 2 Duo ``Allendale'' die size: $111~{\rm mm}^2$, 65 W, 775 pin LGA

    \begin{figure}\centering\includegraphics[]{Figures/lga775t.eps}\end{figure}

    \begin{figure}\centering\includegraphics[]{Figures/lga775b.eps}\end{figure}

  2. Die photomicrograph.

    \begin{figure}\centering\includegraphics[]{Figures/die.eps}\end{figure}

  3. All features/layers are added in separate steps...

    \begin{figure}\centering\includegraphics[height=8.5in]{Figures/icProfile.eps}\end{figure}

  4. It all begins with design, either standard cell, schematic, VHDL, or hand-layout, resulting in a set of masks.

    \begin{figure}\centering\includegraphics[]{Figures/mask.eps}\end{figure}


Thomas P. Kelliher 2009-09-11
Tom Kelliher