Architectural Support for Modern Operating Systems

Tom Kelliher, CS 318

Jan. 23, 1998

Announcements

From last time:

1. OS as interface.

2. Layering and abstractions.

3. Historical developments. Why multiprogram a single user workstation?

Outline:

Assignment

Read Chapter 3.

System Architecture

Consider the contrived organization:

How does the CPU manage all these resources?

What are their relative speeds?

• CPU: 300,000,000 instructions/sec.
• Memory: 10,000,000 word accesses/sec.
• Terminal: 4 characters/sec.
• Disk: 10Mb/sec; 10 ms latency
• Typical network card: 1Mb/sec.
• ``Future'' network cards: 100Mb/sec., 1Gb/sec.

A small example:

1. Ethernet data arriving at 1Gb/sec. with an MTU of 1500. 7E7 packets/sec.

2. 100 instructions in packet interrupt routine.

3. 300MHz processor.

4. 23% of processor cycles needed to handle packets.

I/O Programming

How is data transferred between outside world and memory?

Polling

CPU constantly checks on status of pending I/O device requests.

Consider a kernel level routine for reading a disk block:

int ReadBlock (disk d, char* buffer, int blockNum)
{
   while (d.busy) /* Verify idle */
      /* Go do something else and check back. */

   /* Send read command to disk. */

   while (d.busy)
      /* Go do something else and check back. */

   return d.status;
}

How safe is this? How efficient is it?

Interrupts

1. The I/O device itself signals CPU when an operation completes.

2. Less burden for CPU.

3. Cpu must determine:
   1. Source of interrupt.

   2. Interrupt type.

   3. (Possibly) Transfer data.

4. Byte devices and block devices.

Introduce parallelism into system by decoupling CPU and I/O devices. (Asynchronous vs. synchronous.)

Schema:

1. Start device.
2. Go do something useful.
3. Device signals completion via interrupt.
4. Kernel handles interrupt.

Interrupt Features:

1. Current process is temporarily abandoned --- arbitrary function call.
2. Several priority levels.
3. Most levels can be masked.
4. Several devices can share the same interrupt line. How do we identify the sender?
5. Kernel contains interrupt handlers which service interrupts. How do they identify the device if several exist?
6. After handler finished, unmask interrupts and return to previous process.

DMA

(Direct Memory Access.)

A block I/O device could swamp a CPU forced to perform the actual data transfers.

Solution: Let device access memory and transfer data itself.

Here's what's going on with DMA:

1. CPU reserves an area of memory as a buffer for the I/O (assume a read is performed).

2. CPU loads the base (bottom) address of the buffer into the I/O device.

3. CPU loads the length of the transfer into the I/O device (assume that it's same as the buffer size).

4. Concurrently:
   • CPU goes on to another task (block requesting process).

   • I/O device starts transfer, writes data directly to memory.

   Memory arbitration problems here.

5. I/O device interrupts CPU upon completion.

6. CPU receives interrupt, checks status, schedules formerly blocked process.

Memory and Storage

Storage hierarchy:

1. Registers.

2. Caches.

3. Main Memory.

4. Disk (secondary storage).
   1. Flavors: electronic, magnetic, optical, removable, etc.

5. Tape (tertiary storage).

Hardware Protection

1. Dual mode operation.
2. Privileged instructions.
3. Memory protection mechanisms.
4. Interval timers.

Dual Mode Operation and Privileged Instructions

CPU operates in two states:

1. Supervisor mode
   • All instructions may be executed.
   • This is a privileged mode.
   • Only parts of the OS run in this mode.
   • User threads never run directly in this mode.
2. User mode
   • Some instructions are ``privileged.''
   • Attempt to execute a privileged instruction results in a trap.
   • User threads execute in this mode.

Examples of privileged instructions: I/O instructions, halt, reset, mask interrupts, set interval timer, set status register, and modify page table registers.

Differences, similarities between interrupts, traps, system calls?

Schema of System operation:

1. System powered on; in supervisor mode.
2. System boots, kernel initializes, still in supervisor mode.
3. System enters user mode to run user threads.

Should there be a user mode instruction to enter supervisor mode?

How can supervisor mode be re-entered?

Memory Protection

Prevent thread from scribbling on arbitrary memory locations.

Mechanisms:

1. Bounds registers:
   • Base, limit registers.
   • Base, length registers.
   How does it work?

   

   • Thread 2 running.
   • All generated addresses checked against base, limit.
   • ``Out-of-bounds'' addresses generate traps.

   What needs to be done on a context switch?

2. Virtual memory --- threads run in individual ``virtual'' address spaces.

   Virtual address space mapped onto subset of physical address space:

   

Interval Timers

What prevents a thread from grabbing the CPU and not relinquishing it?

Interval timer, interrupt. On context switch:

1. Set interval time.
2. Run user thread.
3. Timer interrupt generated on timer expiration.
4. Run timer interrupt handler.

Used to:

• Enforce timesharing quantum. Typical quantum: 100 ms.
• Keep time (?!?).

Syscall Mechanism

How does a process perform I/O if it's a privileged operation?