library ieee, lcdf_vhdl; use ieee.std_logic_1164.all, lcdf_vhdl_.func_prims.all; entity EXOR3 is port(i2, i1, i0 : in std_logic; o : out std_logic); end EXOR3; architecture structural of EXOR3 is component NOT1 port(in1 : in std_logic; out1 : out std_logic;); end component; component NAND3 port(in1, in2, in3 : in std_logic; out1 : out std_logic); end component; component NAND4 port(in1, in2, in3, in4 : in std_logic; out1 : out std_logic); end component; signal i2_n, i1_n, i0_n, t3, t2, t1, t0 : std_logic; begin g0: NOT1 port map(i2, i2_n); g1: NOT1 port map(i1, i1_n); g2: NOT1 port map(i0, i0_n); g3: NAND3 port map(i2_n, i1_n, i0, t3); g4: NAND3 port map(i2_n, i1, i0_n, t2); g5: NAND3 port map(i2, i1_n, i0_n, t1); g6: NAND3 port map(i2, i1, i0, t0); g7: NAND4 port map(t3, t2, t1, t0, o); end structural;